1 /******************************************************************************
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2 ** File Name: sdram_sc7710g2.c
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5 ** Copyright: 2013 Spreatrum, Incoporated. All Rights Reserved.
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7 ******************************************************************************/
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8 /******************************************************************************
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10 **-------------------------------------------------------------------------
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11 ** DATE NAME DESCRIPTION
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12 ** 11/03/2013 Create.
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13 ******************************************************************************/
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16 #include <asm/arch/sci_types.h>
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17 #include <asm/arch/arm_reg.h>
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18 #include <asm/arch/sc_reg.h>
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21 #include <asm/arch/sdram_sc7710g2.h>
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22 #include <asm/arch/emc_config.h>
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31 //#define SDRAM_CLK (EMC_CLK/2) // 96MHz
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32 //#define SDRAM_T (1000000000/SDRAM_CLK) // ns
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33 #define SDRAM_T (1000000000/EMC_CLK_400MHZ) // ns
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35 /*******************************************************************************
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36 Variable and Array definiation
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37 *******************************************************************************/
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40 LOCAL CONST EMC_PARAM_T s_emc_parm =
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41 // arm_clk emc_clk ddr driver strength dqs_drv / dat_drv / ctl_drv / clk_drv / clk_wr
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42 //{CHIP_CLK_1000MHZ, EMC_CLK_133MHZ, DDR_DRV_STR_TR_Q, 2, 1, 0, 3, 15}; //EVB
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43 //{CHIP_CLK_1000MHZ, EMC_CLK_400MHZ, DDR_DRV_STR_TR_Q, 2, 2, 0, 2, 15}; // PCB_V1.0.0
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44 {CHIP_CLK_1000MHZ, EMC_CLK_400MHZ, DDR_DRV_STR_TR_Q, 2, 3, 1, 2, 12}; // 4+2 nandmcp
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45 //{CHIP_CLK_1000MHZ, EMC_CLK_333MHZ, DDR_DRV_STR_TR_Q, 1, 1, 1, 2, 19}; // openphone
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49 LOCAL CONST SDRAM_TIMING_PARA_T s_sdram_timing_param =
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50 // ms ns ns ns ns ns ns ns clk clk
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51 // tREF,tRP,tRCD, tWR/tRDL/tDPL,tRFC, tXSR, tRAS, tRRD, tMRD, tWTR(wtr is only for ddr)
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52 #if defined(CHIP0_HYNIX_DDR_H8BCS0RJ0MCP)
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53 {7800, 30, 30, 15, 110, 140, 50, 15, 2, 1 };
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54 #elif defined(CHIP1_TOSHIBA_SDR_TY9000A800JFGP40)
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55 {7800, 23, 23, 2*SDRAM_T, 80, 120, 50, 15, 2, 0 };
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56 #elif defined(CHIP2_ST_SDR_M65K)
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57 {7800, 24, 18, 15, 80, 18, 60, 18, 2, 0 };
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58 #elif defined(CHIP3_SAMSUNG_SDR_K5D1G13DCA)
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59 {7800, 24, 18, 15, 80, 18, 60, 18, 2, 0 };
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60 #elif defined(CHIP4_SAMSUNG_SDR_K5D5657DCBD090)
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61 {7800, 24, 18, 15, 80, 18, 60, 18, 2, 0 };
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62 #elif defined(CHIP5_HYNIX_SDR_HYC0SEH0AF3P)
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63 {7800, 29, 29, 2*SDRAM_T, 80, 2*SDRAM_T, 60, 19, 2, 0 };
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64 #elif defined(CHIP6_SAMSUNG_SDR_K5D1257ACFD090)
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65 {7800, 27, 27, 15, 80, 120, 50, 18, 2, 0 };
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66 #elif defined(CHIP7_HYNIX_SDR_H8ACUOCEOBBR)
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67 {7800, 27, 27, 15, 80, 120, 60, 19, 2, 0 };
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68 #elif defined(CHIP8_HYNIX_SDR_H8ACS0EJ0MCP)
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69 {7800, 27, 27, 15, 80, 120, 60, 19, 2, 0 };
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70 #elif defined(CHIP9_HYNIX_SDR_H8AES0SQ0MCP)
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71 {7800, 27, 27, 15, 80, 120, 60, 19, 2, 0 };
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72 #elif defined(CHIP10_HYNIX_SDR_HYC0SEH0AF3P)
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73 {7800, 27, 27, 15, 80, 120, 60, 19, 2, 0 };
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74 #elif defined(CHIP11_MICRON_SDR_MT48H)
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75 {7800, 20, 20, 15, 100, 120, 60, 2*SDRAM_T,2, 0 };
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76 #elif defined(CHIP12_HYNIX_DDR_H9DA4GH4JJAMCR4EM)
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77 {7800, 30, 30, 15, 90, 140, 50, 15, 2, 2 };
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78 #elif defined(CHIP13_HYNIX_SDR_H8ACS0PH0MCP)
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79 {7800, 27, 27, 15, 80, 120, 60, 19, 2, 0 };
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80 #elif defined(CHIP14_HYNIX_DDR_H9DA4GH2GJAMCR)
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81 {7800, 30, 30, 15, 90, 140, 50, 15, 2, 2 };
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82 #elif defined(CHIP15_SAMSUNG_DDR_K522H1HACF)
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83 {7800, 21, 15, 12, 80, 120, 40, 10, 2, 2 };
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85 {7800, 30, 30, 15, 110, 140, 50, 15, 2, 2 };
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88 #ifndef SDRAM_AUTODETECT_SUPPORT
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90 LOCAL CONST SDRAM_CFG_INFO_T s_sdram_config_info =
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91 #if defined(CHIP0_HYNIX_DDR_H8BCS0RJ0MCP)
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92 {ROW_MODE_13, COL_MODE_10, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, DDR_SDRAM, EMC_ONE_CS_MAP_1GBIT};//for sc7702 emc 16bit, actually this ddr is 32bit
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93 #elif defined(CHIP1_TOSHIBA_SDR_TY9000A800JFGP40)
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94 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_32, BURST_LEN_1_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, SDR_SDRAM, EMC_ONE_CS_MAP_512MBIT};
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95 #elif defined(CHIP2_ST_SDR_M65K)
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96 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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97 #elif defined(CHIP3_SAMSUNG_SDR_K5D1G13DCA)
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98 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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99 #elif defined(CHIP4_SAMSUNG_SDR_K5D5657DCBD090)
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100 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_16, BURST_LEN_8_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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101 #elif defined(CHIP5_HYNIX_SDR_HYC0SEH0AF3P)
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102 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_32, BURST_LEN_8_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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103 #elif defined(CHIP6_SAMSUNG_SDR_K5D1257ACFD090)
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104 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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105 #elif defined(CHIP7_HYNIX_SDR_H8ACUOCEOBBR)
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106 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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107 #elif defined(CHIP8_HYNIX_SDR_H8ACS0EJ0MCP)
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108 {ROW_MODE_13, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_1GBIT};
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109 #elif defined(CHIP9_HYNIX_SDR_H8AES0SQ0MCP)
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110 {ROW_MODE_13, COL_MODE_10, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, SDR_SDRAM, EMC_ONE_CS_MAP_1GBIT};
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111 #elif defined(CHIP10_HYNIX_SDR_HYC0SEH0AF3P)
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112 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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113 #elif defined(CHIP11_MICRON_SDR_MT48H)
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114 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, SDR_SDRAM, EMC_ONE_CS_MAP_256MBIT};
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115 #elif defined(CHIP12_HYNIX_DDR_H9DA4GH4JJAMCR4EM)
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116 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, DDR_SDRAM, EMC_ONE_CS_MAP_2GBIT};
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117 #elif defined(CHIP13_HYNIX_SDR_H8ACS0PH0MCP)
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118 {ROW_MODE_13, COL_MODE_9, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM, EMC_ONE_CS_MAP_512MBIT};
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119 #elif defined(CHIP14_HYNIX_DDR_H9DA4GH2GJAMCR)
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120 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, DDR_SDRAM, EMC_ONE_CS_MAP_2GBIT};
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121 #elif defined(CHIP15_SAMSUNG_DDR_K522H1HACF)
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122 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, DDR_SDRAM, EMC_ONE_CS_MAP_1GBIT};
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124 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG, DDR_SDRAM, EMC_ONE_CS_MAP_1GBIT};
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129 #ifndef SDRAM_AUTODETECT_SUPPORT
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131 LOCAL CONST SDRAM_CHIP_FEATURE_T s_sdram_feature =
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132 #if defined(CHIP0_HYNIX_DDR_H8BCS0RJ0MCP)
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133 { SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT };//for sc7702 emc 512m, actually this ddr is 1g
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134 #elif defined(CHIP1_TOSHIBA_SDR_TY9000A800JFGP40)
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135 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_512M_BIT};
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136 #elif defined(CHIP2_ST_SDR_M65K)
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137 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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138 #elif defined(CHIP3_SAMSUNG_SDR_K5D1G13DCA)
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139 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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140 #elif defined(CHIP4_SAMSUNG_SDR_K5D5657DCBD090)
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141 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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142 #elif defined(CHIP5_HYNIX_SDR_HYC0SEH0AF3P)
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143 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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144 #elif defined(CHIP6_SAMSUNG_SDR_K5D1257ACFD090)
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145 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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146 #elif defined(CHIP7_HYNIX_SDR_H8ACUOCEOBBR)
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147 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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148 #elif defined(CHIP8_HYNIX_SDR_H8ACS0EJ0MCP)
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149 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT };
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150 #elif defined(CHIP9_HYNIX_SDR_H8AES0SQ0MCP)
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151 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT };
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152 #elif defined(CHIP10_HYNIX_SDR_HYC0SEH0AF3P)
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153 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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154 #elif defined(CHIP11_MICRON_SDR_MT48H)
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155 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};
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156 #elif defined(CHIP12_HYNIX_DDR_H9DA4GH4JJAMCR4EM)
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157 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_4G_BIT };
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158 #elif defined(CHIP13_HYNIX_SDR_H8ACS0PH0MCP)
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159 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_512M_BIT};
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160 #elif defined(CHIP14_HYNIX_DDR_H9DA4GH2GJAMCR)
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161 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_2G_BIT };
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162 #elif defined(CHIP15_SAMSUNG_DDR_K522H1HACF)
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163 { SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT };
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165 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT };
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170 CONST EMC_PHY_L1_TIMING_T EMC_PHY_TIMING_L1_INFO[EMC_PHYL1_TIMING_MATRIX_MAX] =
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172 //data_ie, data_oe, dqs_pst_gate, dqs_pre_gate, dqs_ie, dqs_oe
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173 #ifdef SDR_SDRAM_SUPPORT
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174 {0x20, 1, 0, 0, 0, 0}, //sdram cas_latency = 2
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175 {0x40, 1, 0, 0, 0, 0}, //sdram cas_latency = 3
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177 {0xf0, 0xe, 0x10, 0x8, 0xf0, 0xe}, //ddram cas_latency = 2
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178 {0xf0, 0xe, 0x20, 0x10, 0xf0, 0xe}, //ddram cas_latency = 3
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181 CONST EMC_PHY_L2_TIMING_T EMC_PHY_TIMING_L2_INFO[EMC_PHYL2_TIMING_MATRIX_MAX] =
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183 //emc_dl3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19
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184 //{L2_PAR, L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR}, //DLL_OFF
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185 {12,12,12,12, 6, 6, 6, 6, 6, 6, 6, 6, 12, 12, 12, 12, 12, 12, 12, 12}, //DLL_OFF emc=400mhz
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186 {0x8040,0x8040,0x8040,0x8040,0x8020,0x8020,0x8020,0x8020,0x8020,0x8020,0x8020,0x8020,0x8040,0x8040,0x8040,0x8040,0x8040,0x8040,0x8040,0x8040} //DLL_ON
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189 #ifdef SDRAM_AUTODETECT_SUPPORT
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191 CONST SDRAM_MODE_T sdram_mode_table[] =
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193 {CAP_6G_BIT, EMC_ONE_CS_MAP_4GBIT, ROW_MODE_14, ROW_MODE_15_6G, DATA_WIDTH_32},
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194 {CAP_6G_BIT, EMC_ONE_CS_MAP_4GBIT, ROW_MODE_14, COL_MODE_11_6G, DATA_WIDTH_32},
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195 {CAP_4G_BIT, EMC_ONE_CS_MAP_2GBIT, ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32},
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196 {CAP_2G_BIT, EMC_ONE_CS_MAP_2GBIT, ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32},
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197 {CAP_1G_BIT, EMC_ONE_CS_MAP_1GBIT, ROW_MODE_14, COL_MODE_9, DATA_WIDTH_32},
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198 {CAP_1G_BIT, EMC_ONE_CS_MAP_1GBIT, ROW_MODE_13, COL_MODE_10, DATA_WIDTH_32},
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200 {CAP_2G_BIT, EMC_ONE_CS_MAP_2GBIT, ROW_MODE_14, COL_MODE_11, DATA_WIDTH_16},
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201 {CAP_1G_BIT, EMC_ONE_CS_MAP_1GBIT, ROW_MODE_14, COL_MODE_10, DATA_WIDTH_16},
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202 {CAP_ZERO, EMC_ONE_CS_MAP_DEFAULT, SDRAM_MIN_ROW, SDRAM_MIN_COLUMN, DATA_WIDTH_16}
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205 PUBLIC SDRAM_MODE_PTR SDRAM_GetModeTable(void)
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207 return (SDRAM_MODE_PTR)sdram_mode_table;
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210 SDRAM_CFG_INFO_T s_sdram_config_info = {
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216 SDRAM_EXT_MODE_REG,
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218 EMC_ONE_CS_MAP_4GBIT
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224 LOCAL EMC_CHL_INFO_T s_emc_chl_info[] =
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225 {// emc_chl_num axi_chl_wr_pri axi_chl_rd_pri ahb_chl_pri
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226 {EMC_AXI_ARM, EMC_CHL_PRI_2, EMC_CHL_PRI_2, EMC_CHL_NONE},
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227 {EMC_AXI_GPU, EMC_CHL_PRI_0, EMC_CHL_PRI_0, EMC_CHL_NONE},
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228 {EMC_AXI_DISPC, EMC_CHL_PRI_0, EMC_CHL_PRI_3, EMC_CHL_NONE},
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229 {EMC_AHB_CP_MTX, EMC_CHL_NONE, EMC_CHL_NONE, EMC_CHL_PRI_1},
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230 {EMC_AHB_MST_MTX, EMC_CHL_NONE, EMC_CHL_NONE, EMC_CHL_PRI_3},
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231 {EMC_AHB_LCDC, EMC_CHL_NONE, EMC_CHL_NONE, EMC_CHL_PRI_0},
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232 {EMC_AHB_DCAM, EMC_CHL_NONE, EMC_CHL_NONE, EMC_CHL_PRI_2},
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233 {EMC_AHB_VSP, EMC_CHL_NONE, EMC_CHL_NONE, EMC_CHL_PRI_1},
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234 {EMC_CHL_MAX, EMC_CHL_NONE, EMC_CHL_NONE, EMC_CHL_NONE}
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238 PUBLIC EMC_PARAM_PTR EMC_GetPara(void)
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240 return (EMC_PARAM_PTR)&s_emc_parm;
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243 PUBLIC SDRAM_CFG_INFO_T_PTR SDRAM_GetCfg(void)
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245 return (SDRAM_CFG_INFO_T_PTR)&s_sdram_config_info;
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249 PUBLIC SDRAM_TIMING_PARA_T_PTR SDRAM_GetTimingPara(void)
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251 return (SDRAM_TIMING_PARA_T_PTR)&s_sdram_timing_param;
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254 #ifndef SDRAM_AUTODETECT_SUPPORT
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256 PUBLIC SDRAM_CHIP_FEATURE_T_PTR SDRAM_GetFeature(void)
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258 return (SDRAM_CHIP_FEATURE_T_PTR)&s_sdram_feature;
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262 PUBLIC EMC_CHL_INFO_PTR EMC_GetChlInfo(void)
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264 return (EMC_CHL_INFO_PTR)&s_emc_chl_info;
\r