2 * linux/arch/arm/mach-sprd/gpio.c
4 * Generic SPRD GPIO handling
6 * Author: Yingchun Li(yingchun.li@spreadtrum.com)
7 * Created: March 10, 2010
8 * Copyright: Spreadtrum Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 //#include <linux/init.h>
15 //#include <linux/irq.h>
16 //#include <linux/bug.h>
17 //#include <linux/module.h>
18 //#include <linux/delay.h>
20 //#include <asm/gpio.h>
21 #include <asm/arch/gpio.h>
23 //#include <mach/regs_global.h>
24 //#include <mach/regs_gpio.h>
25 //#include <mach/regs_ana.h>
26 #include <asm/arch/sc8810_reg_global.h>
27 #include <asm/arch/sc8810_reg_base.h>
28 #include <asm/arch/gpio_reg_v0.h>
29 #include <asm/arch/gpio_phy.h>
30 #include <asm/arch/asm_generic_gpio.h>
31 #include <asm/arch/regs_ana.h>
32 #include <asm/arch/regs_global.h>
34 #define KERN_WARNING ""
35 #define WARN(nmu, fmt...) printf(fmt)
37 #define BUG_ON(__cond__) if(__cond__) printf("%s line: %d bug on\n", __FUNCTION__, __LINE__)
38 #define pr_err(fmt...) printf(fmt)
39 #define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
40 #define pr_debug(fmt...) printf(fmt)
46 #define GPIO_DBG(fmt...) pr_debug(fmt)
48 #define GPIO_DBG(fmt...)
52 #define GPO_TRI 0xFFFF
56 #define GPO_DATA 0xFFFF
61 enum gpio_section_type gpio_type;
72 #define GPIO_INVALID_ID 0xffff
73 #define INVALID_REG (~(u32)0)
75 //static struct gpio_irq_map gpio_irq_table[NR_GPIO_IRQS];
78 static void __get_gpio_base_info (u32 gpio_id, struct gpio_info *info)
82 struct gpio_section *section_table;
84 section_table = gpio_get_section_table (&table_size);
85 BUG_ON((gpio_id >= GPIO_MAX_PIN_NUM) || (table_size <= 0));
88 info->base_addr = __get_base_addr (gpio_id);
89 info->bit_num = __get_bit_num (gpio_id);
90 info->die = __get_gpio_die(gpio_id);
92 for (i = 0; i < table_size; i++) {
93 if (section_table[i].page_base == info->base_addr) {
94 if (section_table[i].page_size > info->bit_num) {
95 info->gpio_type = section_table[i].section_type;
102 info->gpio_type = GPIO_SECTION_INVALID;
109 static void __gpio_set_dir (struct gpio_info * info, int dir)
115 reg_addr = info->base_addr;
117 switch (info->gpio_type) {
118 case GPIO_SECTION_GPI:
120 WARN(1, "cannot set dir output with GPI");
124 case GPIO_SECTION_GPO:
126 WARN(1, "cannot set dir input with GPO");
130 case GPIO_SECTION_GPIO:
131 reg_addr += GPIO_DIR;
133 case GPIO_SECTION_INVALID:
135 WARN(1, " the GPIO_ID is Invalid in this chip");
139 //local_irq_save(flags);
140 value = gpio_reg_get(reg_addr, info->die);
143 value |= 1 << info->bit_num;
145 value &= ~(1 << info->bit_num);
146 gpio_reg_set(reg_addr, info->die, value);
148 //local_irq_restore(flags);
152 get data register's offset
154 static u32 __gpio_get_data_reg_offs (struct gpio_info *info)
158 switch (info->gpio_type) {
159 case GPIO_SECTION_GPI:
160 offset_addr = GPI_DATA;
162 case GPIO_SECTION_GPO:
163 offset_addr = GPO_DATA;
165 case GPIO_SECTION_GPIO:
166 offset_addr = GPIO_DATA;
168 case GPIO_SECTION_INVALID:
170 pr_err("the GPIO_ID is Invalid in this chip");
178 static int __gpio_get_pin_data (struct gpio_info *info)
183 reg_addr = info->base_addr;
185 offset_addr = __gpio_get_data_reg_offs (info);
187 if (offset_addr != INVALID_REG) {
188 reg_addr += offset_addr;
189 return gpio_reg_get(reg_addr, info->die) & (1<<info->bit_num);
194 static u32 __gpio_get_data_mask_reg_offs (struct gpio_info *info)
198 switch (info->gpio_type) {
199 case GPIO_SECTION_GPI:
200 offset_addr = GPI_DMSK;
202 case GPIO_SECTION_GPO:
203 offset_addr = GPO_TRI;
205 case GPIO_SECTION_GPIO:
206 offset_addr = GPIO_DMSK;
208 case GPIO_SECTION_INVALID:
210 pr_err ("the GPIO_ID is Invalid in this chip");
219 if the data register can be access, return ture, else return false;
221 static int __gpio_get_data_mask (struct gpio_info *info)
227 reg_addr = info->base_addr;
229 offset_addr = __gpio_get_data_mask_reg_offs(info);
230 if (offset_addr != INVALID_REG) {
231 reg_addr += offset_addr;
233 GPIO_DBG("gpio_addr %x data mask :%x\r\n", info->base_addr,
234 gpio_reg_get(reg_addr, info->die));
236 value = gpio_reg_get(reg_addr, info->die);
237 return ( value & (1<< info->bit_num)) ? true : false;
243 static int __gpio_get_dir (struct gpio_info *info)
248 reg_addr = info->base_addr;
250 switch (info->gpio_type) {
251 case GPIO_SECTION_GPI:
254 case GPIO_SECTION_GPO:
257 case GPIO_SECTION_GPIO:
258 reg_addr += GPIO_DIR;
261 case GPIO_SECTION_INVALID:
263 pr_warning("[GPIO_DRV]the GPIO_ID is Invalid in this chip");
268 value = gpio_reg_get(reg_addr, info->die) & (1<< info->bit_num);
269 return value ? true: false;
272 static void __gpio_set_pin_data (struct gpio_info *info ,int b_on)
279 reg_addr = info->base_addr;
281 offset_addr = __gpio_get_data_reg_offs (info);
282 if (offset_addr == INVALID_REG)
285 reg_addr += offset_addr;
287 //local_irq_save(flags);
289 value = gpio_reg_get(reg_addr, info->die);
291 value |= 1 << info->bit_num;
293 value &= ~(1 << info->bit_num);
294 gpio_reg_set(reg_addr, info->die, value);
295 //local_irq_restore(flags);
299 set data mask, the gpio data register can be access
301 static void __gpio_set_data_mask (struct gpio_info *info, int b_on)
308 reg_addr = info->base_addr;
309 offset_addr = __gpio_get_data_mask_reg_offs(info);
310 if (offset_addr != INVALID_REG) {
311 reg_addr += offset_addr;
313 //local_irq_save(flags);
314 value = gpio_reg_get(reg_addr, info->die);
316 value |= 1 << info->bit_num;
318 value &= ~(1 << info->bit_num);
319 gpio_reg_set(reg_addr, info->die, value);
320 //local_irq_restore(flags);
322 GPIO_DBG("After setting gpio_addr %x data mask :%x\r\n", reg_addr,
323 gpio_reg_get(reg_addr, info->die));
329 int sprd_gpio_direction_output(struct gpio_chip *chip,
330 unsigned offset, int value)
332 unsigned gpio_id = offset;
333 struct gpio_info gpio_info;
335 __get_gpio_base_info (gpio_id, &gpio_info);
336 __gpio_set_dir(&gpio_info, 1);
337 __gpio_set_pin_data(&gpio_info, value);
341 int sprd_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
343 unsigned gpio_id = offset;
344 struct gpio_info gpio_info;
346 __get_gpio_base_info (gpio_id, &gpio_info);
347 __gpio_set_dir(&gpio_info, 0);
354 int sprd_gpio_get(struct gpio_chip *chip, unsigned offset)
356 unsigned gpio_id = offset;
357 struct gpio_info gpio_info;
359 __get_gpio_base_info (gpio_id, &gpio_info);
361 if (!__gpio_get_data_mask (&gpio_info)) {
362 WARN(1, "GPIO_%d data mask hasn't been opened!\n", gpio_id);
365 if (__gpio_get_dir (&gpio_info))
367 WARN(1, "[GPIO_DRV]GPIO_GetValue: GPIO_%d should be input port!\n", gpio_id);
370 return __gpio_get_pin_data (&gpio_info);
376 * Set output GPIO level
378 static void sprd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
380 struct gpio_info gpio_info;
381 u32 gpio_id = offset;
383 BUG_ON (gpio_id >= GPIO_MAX_PIN_NUM);
385 __get_gpio_base_info (gpio_id, &gpio_info);
388 if (!__gpio_get_data_mask (&gpio_info))
390 WARN(1, "GPIO_%d data mask no opened!", gpio_id);
394 if (!__gpio_get_dir (&gpio_info)) {
395 WARN(1, "GPIO_%d dir wrong!can't set input value", gpio_id);
399 __gpio_set_pin_data (&gpio_info, value);
401 GPIO_DBG("gpio_%d setting :%x \n", gpio_id, value);
404 int sprd_gpio_request(struct gpio_chip *chip, unsigned offset)
406 unsigned gpio_id = offset;
407 struct gpio_info gpio_info;
409 GPIO_DBG("request gpio_%d\r\n", gpio_id);
410 __get_gpio_base_info (gpio_id, &gpio_info);
412 GPIO_DBG("gpio info, pin is :%d, base addr :%x, bit num :%d, type :%d\r\n", gpio_id,
413 gpio_info.base_addr, gpio_info.bit_num, gpio_info.gpio_type);
414 GPIO_DBG("ture is %d, false is %d\n", true, false);
415 __gpio_set_data_mask (&gpio_info, true);
420 static void sprd_gpio_free(struct gpio_chip *chip, unsigned offset)
422 unsigned gpio_id = offset;
423 struct gpio_info gpio_info;
425 if (gpio_id > GPIO_MAX_PIN_NUM) {
426 WARN(1, KERN_WARNING"gpio number is too larger:%d\r\n", gpio_id);
430 __get_gpio_base_info (gpio_id, &gpio_info);
431 __gpio_set_data_mask (&gpio_info, false);
437 static int sprd_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
441 for (i = 0; i < NR_GPIO_IRQS; i++) {
442 if (gpio_irq_table[i].gpio_id == offset)
446 if (i >= NR_GPIO_IRQS)
448 return gpio_irq_table[i].irq_num;
451 int irq_to_gpio(unsigned long irq)
455 for (i = 0; i < NR_GPIO_IRQS; i++) {
456 if (gpio_irq_table[i].irq_num == irq)
460 if (i >= NR_GPIO_IRQS)
462 return gpio_irq_table[i].gpio_id;
464 EXPORT_SYMBOL(irq_to_gpio);
466 static struct gpio_chip sprd_gpio_chip = {
467 .label = "sc8800s-gpio",
468 .direction_input = sprd_gpio_direction_input,
469 .direction_output = sprd_gpio_direction_output,
470 .get = sprd_gpio_get,
471 .set = sprd_gpio_set,
472 .request = sprd_gpio_request,
473 .free = sprd_gpio_free,
474 .to_irq = sprd_gpio_to_irq,
476 .ngpio = GPIO_MAX_PIN_NUM,
479 static u32 __gpio_get_int_mask_addr (struct gpio_info *info)
483 switch (info->gpio_type) {
484 case GPIO_SECTION_GPI:
485 offset_addr = GPI_IE;
487 case GPIO_SECTION_GPO:
488 WARN(1, "this opretion can not belong to GPO");
491 case GPIO_SECTION_GPIO:
492 offset_addr = GPIO_IE;
495 case GPIO_SECTION_INVALID:
497 WARN (1, "the GPIO_ID is Invalid in this chip");
506 static void __gpio_enable_irq (struct gpio_info *info)
513 reg_addr = info->base_addr;
514 offset_addr = __gpio_get_int_mask_addr (info);
515 if (offset_addr != INVALID_REG) {
516 reg_addr += offset_addr;
517 local_irq_save(flags);
518 value = gpio_reg_get(reg_addr, info->die);
519 value |= 1 << info->bit_num;
520 gpio_reg_set(reg_addr, info->die, value);
521 local_irq_restore(flags);
527 static void __gpio_disable_irq (struct gpio_info *info)
534 reg_addr = info->base_addr;
535 offset_addr = __gpio_get_int_mask_addr (info);
537 if (offset_addr != INVALID_REG) {
538 reg_addr += offset_addr;
539 local_irq_save(flags);
540 value = gpio_reg_get(reg_addr, info->die);
541 value &= ~ (1 << info->bit_num);
542 gpio_reg_set(reg_addr, info->die, value);
543 local_irq_restore(flags);
550 static void __gpio_clear_irq_status (struct gpio_info *info)
556 reg_addr = info->base_addr;
558 switch (info->gpio_type) {
559 case GPIO_SECTION_GPI:
562 case GPIO_SECTION_GPO:
563 GPIO_DBG("this opretion can not belong to GPO");
565 case GPIO_SECTION_GPIO:
568 case GPIO_SECTION_INVALID:
570 GPIO_DBG("the GPIO_ID is Invalid in this chip");
575 local_irq_save(flags);
576 value = gpio_reg_get(reg_addr, info->die);
577 value &= ~ (1 << info->bit_num);
578 value |= 1 << info->bit_num;
579 gpio_reg_set(reg_addr, info->die, value);
582 static int __gpio_get_int_status (struct gpio_info *info)
587 reg_addr = info->base_addr;
589 switch (info->gpio_type) {
590 case GPIO_SECTION_GPI:
593 case GPIO_SECTION_GPO:
594 WARN(1, "The corresponding reg of this GPIO_ID is a GPO! No Intr!");
597 case GPIO_SECTION_GPIO:
598 reg_addr += GPIO_MIS;
600 case GPIO_SECTION_INVALID:
602 WARN(1, "the GPIO_ID is Invalid in this chip");
606 value = gpio_reg_get(reg_addr, info->die);
608 return ( value & (1 << info->bit_num)) ? true : false;
611 static void __gpio_set_int_type (struct gpio_info *info, int type)
613 if (info->gpio_type == GPIO_SECTION_GPI) {
615 case IRQ_TYPE_LEVEL_HIGH: // detect high level.
616 gpio_reg_or( (info->base_addr + GPI_IEV), info->die,
617 (0x1 << info->bit_num));
620 case IRQ_TYPE_LEVEL_LOW: // detect low level.
621 gpio_reg_and( (info->base_addr + GPI_IEV), info->die,
622 ~ (0x1 << info->bit_num));
625 case IRQ_TYPE_EDGE_BOTH: // detect the rising edges and falling edges.
626 case IRQ_TYPE_EDGE_RISING: // detect the rising edges.
627 case IRQ_TYPE_EDGE_FALLING:
629 WARN(1, "The Irq type is invalid for GPI. \n");
632 } else if (info->gpio_type == GPIO_SECTION_GPIO) {
634 case IRQ_TYPE_LEVEL_HIGH: // detect high level.
635 gpio_reg_or( (info->base_addr + GPIO_IS), info->die, (0x1 << info->bit_num));
636 gpio_reg_and(info->base_addr + GPIO_IBE, info->die, ~ (0x1 << info->bit_num));
637 gpio_reg_or( (info->base_addr + GPIO_IEV), info->die, (0x1 << info->bit_num));
640 case IRQ_TYPE_LEVEL_LOW: // detect low level.
641 gpio_reg_or( (info->base_addr + GPIO_IS), info->die, (0x1 << info->bit_num));
642 gpio_reg_and(info->base_addr + GPIO_IBE, info->die, ~ (0x1 << info->bit_num));
643 gpio_reg_and( (info->base_addr + GPIO_IEV), info->die, ~(0x1 << info->bit_num));
646 case IRQ_TYPE_EDGE_BOTH: // detect the rising edges and falling edges.
647 gpio_reg_and( (info->base_addr + GPIO_IS), info->die, ~(0x1 << info->bit_num));
648 gpio_reg_or(info->base_addr + GPIO_IBE, info->die, (0x1 << info->bit_num));
649 gpio_reg_and( (info->base_addr + GPIO_IEV), info->die, ~(0x1 << info->bit_num));
652 case IRQ_TYPE_EDGE_RISING: // detect the rising edges.
653 gpio_reg_and( (info->base_addr + GPIO_IS), info->die, ~(0x1 << info->bit_num));
654 gpio_reg_and(info->base_addr + GPIO_IBE, info->die, ~ (0x1 << info->bit_num));
655 gpio_reg_or( (info->base_addr + GPIO_IEV), info->die, (0x1 << info->bit_num));
658 case IRQ_TYPE_EDGE_FALLING:
659 gpio_reg_and( (info->base_addr + GPIO_IS), info->die, ~(0x1 << info->bit_num));
660 gpio_reg_and(info->base_addr + GPIO_IBE, info->die, ~ (0x1 << info->bit_num));
661 gpio_reg_and( (info->base_addr + GPIO_IEV), info->die, ~(0x1 << info->bit_num));
664 WARN(1, "fault irq type \r\n");
668 WARN(1, "the gpio type is Invalid for irq\r\n");
674 The GPI module can do handware debouce, the max period is 255ms,
676 if your application need debounce time larger than that, please use software
679 void gpio_set_hw_debounce (unsigned int gpio, u8 period)
683 struct gpio_info gpio_info;
686 __get_gpio_base_info (gpio, &gpio_info);
687 if (gpio_info.gpio_type != GPIO_SECTION_GPI) {
688 WARN(1, "GPIO_%d is not in GPI\r\n", gpio);
692 reg_addr = gpio_info.base_addr;
693 reg_addr += (GPI_0CTRL+ (gpio_info.bit_num << 2));
695 local_irq_save(flags);
698 GPIO_REG_OR (reg_addr, GPI_DEBOUNCE_BIT);
699 GPIO_REG_SET (reg_addr, (GPIO_REG32 (reg_addr) & 0xFF00) +debounce_period);
701 gpio_reg_or(reg_addr, gpio_info.die, GPI_DEBOUNCE_BIT);
702 value = (gpio_reg_get(reg_addr, gpio_info.die) & 0xFF00) + period;
703 gpio_reg_set(reg_addr, gpio_info.die, value);
704 } else {// not recommend
705 //GPIO_REG_AND (reg_addr, ~GPI_DEBOUNCE_BIT); //bypass mode
706 gpio_reg_and(reg_addr, gpio_info.die, ~GPI_DEBOUNCE_BIT);
708 local_irq_restore(flags);
711 EXPORT_SYMBOL(gpio_set_hw_debounce);
714 generate the trig_start pulse for GPI interrupt;
716 static void __gpio_trig_detect (struct gpio_info *info)
722 reg_addr = info->base_addr;
724 switch (info->gpio_type) {
725 case GPIO_SECTION_GPI:
726 reg_addr += GPI_TRIG;
729 case GPIO_SECTION_GPO:
730 case GPIO_SECTION_GPIO:
731 GPIO_DBG("[GPIO_DRV]this opretion can not belong to GPO/GPIO");
735 case GPIO_SECTION_INVALID:
737 GPIO_DBG ("[GPIO_DRV]the GPIO_ID is Invalid in this chip");
742 local_irq_save(flags);
744 value = gpio_reg_get(reg_addr, info->die) & ~(1 << info->bit_num);
745 value |= 1 << info->bit_num;
746 gpio_reg_set(reg_addr, info->die, value);
748 local_irq_restore(flags);
749 //GPIO_REG_SET (reg_addr, ( (GPIO_REG32 (reg_addr) & ~ (1<<pGpio_info->bit_num)) | (value<<pGpio_info->bit_num)));
754 void gpio_enable_gpi_interupt (struct gpio_info *info)
757 switch (info->gpio_type) {
758 case GPIO_SECTION_GPI:
759 __gpio_enable_irq (info);
760 __gpio_trig_detect (info);
762 case GPIO_SECTION_GPO:
763 case GPIO_SECTION_GPIO:
772 //EXPORT_SYMBOL(gpio_enable_gpi_interupt);
774 static void sprd_ack_gpio_irq(unsigned int irq)
777 struct gpio_irq_map *map= get_irq_chip_data(irq);
778 struct gpio_info gpio_info;
781 if (gpio >= GPIO_MAX_PIN_NUM ) {
782 pr_warning(" [%s] error gpio %d\n", __FUNCTION__, gpio);
785 GPIO_DBG("ack irq gpio %d irq %d", gpio, irq);
787 __get_gpio_base_info (gpio, &gpio_info);
788 __gpio_clear_irq_status(&gpio_info);
791 static void sprd_mask_gpio_irq(unsigned int irq)
794 struct gpio_irq_map *map= get_irq_chip_data(irq);
795 struct gpio_info gpio_info;
798 if (gpio >= GPIO_MAX_PIN_NUM ) {
799 pr_warning(" [%s] error gpio %d\n", __func__, gpio);
803 GPIO_DBG("mask gpio %d irq %d", gpio, irq);
804 __get_gpio_base_info (gpio, &gpio_info);
805 __gpio_disable_irq (&gpio_info);
809 static void sprd_unmask_gpio_irq(unsigned int irq)
812 struct gpio_info gpio_info;
813 struct gpio_irq_map *map= get_irq_chip_data(irq);
816 if (gpio >= GPIO_MAX_PIN_NUM ) {
817 pr_warning(" [%s] error gpio %d\n", __FUNCTION__, gpio);
821 GPIO_DBG("unmask gpio %d irq %d", gpio, irq);
822 __get_gpio_base_info (gpio, &gpio_info);
823 __gpio_enable_irq (&gpio_info);
825 if(gpio_info.gpio_type == GPIO_SECTION_GPI)
826 __gpio_trig_detect (&gpio_info);
830 static int sprd_gpio_irq_type(unsigned int irq, unsigned int type)
833 struct gpio_irq_map *map= get_irq_chip_data(irq);
834 struct gpio_info gpio_info;
837 if (gpio >= GPIO_MAX_PIN_NUM ) {
838 pr_warning(" [%s] error gpio %d\n", __FUNCTION__, gpio);
842 __get_gpio_base_info (gpio, &gpio_info);
844 __gpio_set_int_type(&gpio_info, type);
846 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
847 __set_irq_handler_unlocked(irq, handle_level_irq);
848 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
849 __set_irq_handler_unlocked(irq, handle_edge_irq);
853 static void sprd_disable_gpio_irq(unsigned int irq)
855 sprd_mask_gpio_irq(irq);
857 static struct irq_chip sprd_muxed_gpio_chip = {
859 .ack = sprd_ack_gpio_irq,
860 .mask = sprd_mask_gpio_irq,
861 .unmask = sprd_unmask_gpio_irq,
862 .set_type = sprd_gpio_irq_type,
863 .disable = sprd_disable_gpio_irq,
866 static int gpio_get_int_status(unsigned int gpio)
868 struct gpio_info gpio_info;
870 __get_gpio_base_info (gpio, &gpio_info);
871 return __gpio_get_int_status (&gpio_info);
876 static void sprd_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
880 for (i = 0; i < NR_GPIO_IRQS; i++) {
881 if (gpio_irq_table[i].gpio_id == GPIO_INVALID_ID) {
884 if (gpio_get_int_status(gpio_irq_table[i].gpio_id)) {
885 generic_handle_irq(gpio_irq_table[i].irq_num);
889 static void sprd_gpio_irq_init(void)
894 for(i = 0; i < NR_GPIO_IRQS; i++) {
895 gpio_irq_table[i].gpio_id= GPIO_INVALID_ID;
897 for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + NR_GPIO_IRQS); irq++) {
898 set_irq_chip(irq, &sprd_muxed_gpio_chip);
899 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
902 set_irq_chained_handler(IRQ_GPIO_INT, sprd_gpio_demux_handler);
903 set_irq_chained_handler(IRQ_ANA_GPIO_INT, sprd_gpio_demux_handler);
907 allocate an irq for gpio
909 __must_check int sprd_alloc_gpio_irq(unsigned gpio)
913 struct gpio_info gpio_info;
916 __get_gpio_base_info (gpio, &gpio_info);
918 // find a free record
919 for (i = 0; i< NR_GPIO_IRQS; i++) {
920 if (gpio_irq_table[i].gpio_id == gpio) {
921 pr_warning("irq for GPIO_%d has been alloc !\n", gpio);
926 for(i = 0; i < NR_GPIO_IRQS; i++) {
927 if (gpio_irq_table[i].gpio_id == GPIO_INVALID_ID)
931 if (i >= NR_GPIO_IRQS) {
932 // No free item in the table.
935 local_irq_save(flags);
936 irq = GPIO_IRQ_START + i;
937 gpio_irq_table[i].gpio_id = gpio;
938 gpio_irq_table[i].irq_num = irq;
940 set_irq_chip_data(irq, &gpio_irq_table[i]);
941 local_irq_restore(flags);
942 __gpio_clear_irq_status(&gpio_info);
943 if (gpio_info.gpio_type == GPIO_SECTION_GPI)
944 __gpio_trig_detect (&gpio_info);
949 EXPORT_SYMBOL(sprd_alloc_gpio_irq);
951 void sprd_free_gpio_irq(int irq)
956 local_irq_save(flags);
957 for (i = 0; i < NR_GPIO_IRQS; i++) {
958 if (gpio_irq_table[i].irq_num == irq) {
959 set_irq_chip_data(irq, NULL);
960 gpio_irq_table[i].gpio_id = GPIO_INVALID_ID;
964 local_irq_restore(flags);
966 EXPORT_SYMBOL(sprd_free_gpio_irq);
968 __init void sprd_gpio_init(void)
970 //enable gpio bank 0~10, that is, all 176 gpio
971 //__raw_writel(0x7fff, GR_GEN2);
972 //CHIP_REG_OR ( (GR_GEN0), (GEN0_GPIO_EN | GEN0_GPIO_RTC_EN));
973 __raw_bits_or (GEN0_GPIO_EN | GEN0_GPIO_RTC_EN, GR_GEN0);
974 ANA_REG_OR (ANA_AGEN,AGEN_RTC_GPIO_EN);
976 ANA_REG_OR (ANA_AGEN,AGEN_GPIO_EN);
978 gpiochip_add(&sprd_gpio_chip);
980 sprd_gpio_irq_init();
983 void sprd_gpio_init(void)
985 //enable gpio bank 0~10, that is, all 176 gpio
986 //__raw_writel(0x7fff, GR_GEN2);
987 //CHIP_REG_OR ( (GR_GEN0), (GEN0_GPIO_EN | GEN0_GPIO_RTC_EN));
988 // __raw_bits_or (GEN0_GPIO_EN | GEN0_GPIO_RTC_EN, GR_GEN0);
990 temp = readl(GR_GEN0);
991 temp |= (GEN0_GPIO_EN);
992 writel(temp, GR_GEN0);
996 ANA_REG_OR (ANA_APB_CLK_EN,GPIO_EB);
998 //gpiochip_add(&sprd_gpio_chip);
1000 // sprd_gpio_irq_init();