arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <asm/emif.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 /*
  18  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  19  * EVM. Since the parts used and geometry are identical for
  20  * evm for a given OMAP5 revision, this information is kept
  21  * here instead of being in board directory. However the key functions
  22  * exported are weakly linked so that they can be over-ridden in the board
  23  * directory if there is a OMAP5 board in the future that uses a different
  24  * memory device or geometry.
  25  *
  26  * For any new board with different memory devices over-ride one or more
  27  * of the following functions as per the CONFIG flags you intend to enable:
  28  * - emif_get_reg_dump()
  29  * - emif_get_dmm_regs()
  30  * - emif_get_device_details()
  31  * - emif_get_device_timings()
  32  */
  33
  34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  35 const struct emif_regs emif_regs_532_mhz_2cs = {
  36         .sdram_config_init              = 0x80800EBA,
  37         .sdram_config                   = 0x808022BA,
  38         .ref_ctrl                       = 0x0000081A,
  39         .sdram_tim1                     = 0x772F6873,
  40         .sdram_tim2                     = 0x304a129a,
  41         .sdram_tim3                     = 0x02f7e45f,
  42         .read_idle_ctrl                 = 0x00050000,
  43         .zq_config                      = 0x000b3215,
  44         .temp_alert_config              = 0x08000a05,
  45         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  46         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  47         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  48         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  49         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  50         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  51         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  52 };
  53
  54 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  55         .sdram_config_init              = 0x80800EBA,
  56         .sdram_config                   = 0x808022BA,
  57         .ref_ctrl                       = 0x0000081A,
  58         .sdram_tim1                     = 0x772F6873,
  59         .sdram_tim2                     = 0x304a129a,
  60         .sdram_tim3                     = 0x02f7e45f,
  61         .read_idle_ctrl                 = 0x00050000,
  62         .zq_config                      = 0x100b3215,
  63         .temp_alert_config              = 0x08000a05,
  64         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  65         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  66         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  67         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  68         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  69         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  70         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  71 };
  72
  73 const struct emif_regs emif_regs_266_mhz_2cs = {
  74         .sdram_config_init              = 0x80800EBA,
  75         .sdram_config                   = 0x808022BA,
  76         .ref_ctrl                       = 0x0000040D,
  77         .sdram_tim1                     = 0x2A86B419,
  78         .sdram_tim2                     = 0x1025094A,
  79         .sdram_tim3                     = 0x026BA22F,
  80         .read_idle_ctrl                 = 0x00050000,
  81         .zq_config                      = 0x000b3215,
  82         .temp_alert_config              = 0x08000a05,
  83         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  84         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  85         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  86         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  87         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  88         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  89         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  90 };
  91
  92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  93         .sdram_config_init              = 0x61851B32,
  94         .sdram_config                   = 0x61851B32,
  95         .sdram_config2                  = 0x0,
  96         .ref_ctrl                       = 0x00001035,
  97         .sdram_tim1                     = 0xCCCF36B3,
  98         .sdram_tim2                     = 0x308F7FDA,
  99         .sdram_tim3                     = 0x027F88A8,
 100         .read_idle_ctrl                 = 0x00050000,
 101         .zq_config                      = 0x0007190B,
 102         .temp_alert_config              = 0x00000000,
 103         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 104         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 105         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 106         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 107         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 108         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 109         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 110         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 111         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 112         .emif_rd_wr_lvl_ctl             = 0x00000000,
 113         .emif_rd_wr_exec_thresh         = 0x00000305
 114 };
 115
 116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 117         .sdram_config_init              = 0x61851B32,
 118         .sdram_config                   = 0x61851B32,
 119         .sdram_config2                  = 0x0,
 120         .ref_ctrl                       = 0x00001035,
 121         .sdram_tim1                     = 0xCCCF36B3,
 122         .sdram_tim2                     = 0x308F7FDA,
 123         .sdram_tim3                     = 0x027F88A8,
 124         .read_idle_ctrl                 = 0x00050000,
 125         .zq_config                      = 0x1007190B,
 126         .temp_alert_config              = 0x00000000,
 127         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 128         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 129         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 130         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 131         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 132         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 133         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 134         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 135         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 136         .emif_rd_wr_lvl_ctl             = 0x00000000,
 137         .emif_rd_wr_exec_thresh         = 0x40000305
 138 };
 139
 140 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 141         .sdram_config_init              = 0x61851ab2,
 142         .sdram_config                   = 0x61851ab2,
 143         .sdram_config2                  = 0x08000000,
 144         .ref_ctrl                       = 0x000040F1,
 145         .ref_ctrl_final                 = 0x00001035,
 146         .sdram_tim1                     = 0xCCCF36B3,
 147         .sdram_tim2                     = 0x308F7FDA,
 148         .sdram_tim3                     = 0x027F88A8,
 149         .read_idle_ctrl                 = 0x00050001,
 150         .zq_config                      = 0x0007190B,
 151         .temp_alert_config              = 0x00000000,
 152         .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
 153         .emif_ddr_phy_ctlr_1            = 0x0E24400A,
 154         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 155         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 156         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 157         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 158         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 159         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 160         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 161         .emif_rd_wr_lvl_ctl             = 0x00000000,
 162         .emif_rd_wr_exec_thresh         = 0x00000305
 163 };
 164
 165 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 166         .sdram_config_init              = 0x61851B32,
 167         .sdram_config                   = 0x61851B32,
 168         .sdram_config2                  = 0x08000000,
 169         .ref_ctrl                       = 0x000040F1,
 170         .ref_ctrl_final                 = 0x00001035,
 171         .sdram_tim1                     = 0xCCCF36B3,
 172         .sdram_tim2                     = 0x308F7FDA,
 173         .sdram_tim3                     = 0x027F88A8,
 174         .read_idle_ctrl                 = 0x00050001,
 175         .zq_config                      = 0x0007190B,
 176         .temp_alert_config              = 0x00000000,
 177         .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
 178         .emif_ddr_phy_ctlr_1            = 0x0E24400A,
 179         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 180         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 181         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 182         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 183         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 184         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 185         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 186         .emif_rd_wr_lvl_ctl             = 0x00000000,
 187         .emif_rd_wr_exec_thresh         = 0x00000305
 188 };
 189
 190 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 191         .sdram_config_init              = 0x61862B32,
 192         .sdram_config                   = 0x61862B32,
 193         .sdram_config2                  = 0x08000000,
 194         .ref_ctrl                       = 0x0000493E,
 195         .ref_ctrl_final                 = 0x0000144A,
 196         .sdram_tim1                     = 0xD113781C,
 197         .sdram_tim2                     = 0x308F7FE3,
 198         .sdram_tim3                     = 0x009F86A8,
 199         .read_idle_ctrl                 = 0x00050000,
 200         .zq_config                      = 0x0007190B,
 201         .temp_alert_config              = 0x00000000,
 202         .emif_ddr_phy_ctlr_1_init       = 0x0E24400D,
 203         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 204         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 205         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 206         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 207         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 208         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 209         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 210         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 211         .emif_rd_wr_lvl_ctl             = 0x00000000,
 212         .emif_rd_wr_exec_thresh         = 0x00000305
 213 };
 214
 215 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 216         .dmm_lisa_map_0 = 0x0,
 217         .dmm_lisa_map_1 = 0x0,
 218         .dmm_lisa_map_2 = 0x80740300,
 219         .dmm_lisa_map_3 = 0xFF020100,
 220         .is_ma_present  = 0x1
 221 };
 222
 223 /*
 224  * DRA752 EVM board has 1.5 GB of memory
 225  * EMIF1 --> 2Gb * 2 =  512MB
 226  * EMIF2 --> 2Gb * 4 =  1GB
 227  * so mapping 1GB interleaved and 512MB non-interleaved
 228  */
 229 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 230         .dmm_lisa_map_0 = 0x0,
 231         .dmm_lisa_map_1 = 0x80640300,
 232         .dmm_lisa_map_2 = 0xC0500220,
 233         .dmm_lisa_map_3 = 0xFF020100,
 234         .is_ma_present  = 0x1
 235 };
 236
 237 /*
 238  * DRA752 EVM EMIF1 ONLY CONFIGURATION
 239  */
 240 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 241         .dmm_lisa_map_0 = 0x0,
 242         .dmm_lisa_map_1 = 0x0,
 243         .dmm_lisa_map_2 = 0x80500100,
 244         .dmm_lisa_map_3 = 0xFF020100,
 245         .is_ma_present  = 0x1
 246 };
 247
 248 /*
 249  * DRA752 EVM EMIF2 ONLY CONFIGURATION
 250  */
 251 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 252         .dmm_lisa_map_0 = 0x0,
 253         .dmm_lisa_map_1 = 0x0,
 254         .dmm_lisa_map_2 = 0x80600200,
 255         .dmm_lisa_map_3 = 0xFF020100,
 256         .is_ma_present  = 0x1
 257 };
 258
 259 /*
 260  * DRA722 EVM EMIF1 CONFIGURATION
 261  */
 262 const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 263         .dmm_lisa_map_0 = 0x0,
 264         .dmm_lisa_map_1 = 0x0,
 265         .dmm_lisa_map_2 = 0x80600100,
 266         .dmm_lisa_map_3 = 0xFF020100,
 267         .is_ma_present  = 0x1
 268 };
 269
 270 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 271 {
 272         switch (omap_revision()) {
 273         case OMAP5430_ES1_0:
 274                 *regs = &emif_regs_532_mhz_2cs;
 275                 break;
 276         case OMAP5432_ES1_0:
 277                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 278                 break;
 279         case OMAP5430_ES2_0:
 280                 *regs = &emif_regs_532_mhz_2cs_es2;
 281                 break;
 282         case OMAP5432_ES2_0:
 283                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 284                 break;
 285         case DRA752_ES1_0:
 286         case DRA752_ES1_1:
 287                 switch (emif_nr) {
 288                 case 1:
 289                         *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 290                         break;
 291                 case 2:
 292                         *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
 293                         break;
 294                 }
 295                 break;
 296         case DRA722_ES1_0:
 297                 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 298                 break;
 299         default:
 300                 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 301         }
 302 }
 303
 304 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 305         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 306
 307 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 308                                                 **dmm_lisa_regs)
 309 {
 310         switch (omap_revision()) {
 311         case OMAP5430_ES1_0:
 312         case OMAP5430_ES2_0:
 313         case OMAP5432_ES1_0:
 314         case OMAP5432_ES2_0:
 315                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 316                 break;
 317         case DRA752_ES1_0:
 318         case DRA752_ES1_1:
 319                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 320                 break;
 321         case DRA722_ES1_0:
 322         default:
 323                 *dmm_lisa_regs = &lisa_map_2G_x_2;
 324         }
 325
 326 }
 327
 328 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 329         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 330 #else
 331
 332 static const struct lpddr2_device_details dev_4G_S4_details = {
 333         .type           = LPDDR2_TYPE_S4,
 334         .density        = LPDDR2_DENSITY_4Gb,
 335         .io_width       = LPDDR2_IO_WIDTH_32,
 336         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 337 };
 338
 339 static void emif_get_device_details_sdp(u32 emif_nr,
 340                 struct lpddr2_device_details *cs0_device_details,
 341                 struct lpddr2_device_details *cs1_device_details)
 342 {
 343         /* EMIF1 & EMIF2 have identical configuration */
 344         *cs0_device_details = dev_4G_S4_details;
 345         *cs1_device_details = dev_4G_S4_details;
 346 }
 347
 348 void emif_get_device_details(u32 emif_nr,
 349                 struct lpddr2_device_details *cs0_device_details,
 350                 struct lpddr2_device_details *cs1_device_details)
 351         __attribute__((weak, alias("emif_get_device_details_sdp")));
 352
 353 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 354
 355 const u32 ext_phy_ctrl_const_base[] = {
 356         0x01004010,
 357         0x00001004,
 358         0x04010040,
 359         0x01004010,
 360         0x00001004,
 361         0x00000000,
 362         0x00000000,
 363         0x00000000,
 364         0x80080080,
 365         0x00800800,
 366         0x08102040,
 367         0x00000001,
 368         0x540A8150,
 369         0xA81502a0,
 370         0x002A0540,
 371         0x00000000,
 372         0x00000000,
 373         0x00000000,
 374         0x00000077,
 375         0x0
 376 };
 377
 378 const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 379         0x01004010,
 380         0x00001004,
 381         0x04010040,
 382         0x01004010,
 383         0x00001004,
 384         0x00000000,
 385         0x00000000,
 386         0x00000000,
 387         0x80080080,
 388         0x00800800,
 389         0x08102040,
 390         0x00000002,
 391         0x0,
 392         0x0,
 393         0x0,
 394         0x00000000,
 395         0x00000000,
 396         0x00000000,
 397         0x00000057,
 398         0x0
 399 };
 400
 401 const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 402         0x50D4350D,
 403         0x00000D43,
 404         0x04010040,
 405         0x01004010,
 406         0x00001004,
 407         0x00000000,
 408         0x00000000,
 409         0x00000000,
 410         0x80080080,
 411         0x00800800,
 412         0x08102040,
 413         0x00000002,
 414         0x00000000,
 415         0x00000000,
 416         0x00000000,
 417         0x00000000,
 418         0x00000000,
 419         0x00000000,
 420         0x00000057,
 421         0x0
 422 };
 423
 424 const u32
 425 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 426         0x00980098,
 427         0x00340034,
 428         0x00350035,
 429         0x00340034,
 430         0x00310031,
 431         0x00340034,
 432         0x007F007F,
 433         0x007F007F,
 434         0x007F007F,
 435         0x007F007F,
 436         0x007F007F,
 437         0x00480048,
 438         0x004A004A,
 439         0x00520052,
 440         0x00550055,
 441         0x00500050,
 442         0x00000000,
 443         0x00600020,
 444         0x40010080,
 445         0x08102040,
 446         0x0,
 447         0x0,
 448         0x0,
 449         0x0,
 450         0x0
 451 };
 452
 453 const u32
 454 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 455         0x00980098,
 456         0x00330033,
 457         0x00330033,
 458         0x002F002F,
 459         0x00320032,
 460         0x00310031,
 461         0x007F007F,
 462         0x007F007F,
 463         0x007F007F,
 464         0x007F007F,
 465         0x007F007F,
 466         0x00520052,
 467         0x00520052,
 468         0x00470047,
 469         0x00490049,
 470         0x00500050,
 471         0x00000000,
 472         0x00600020,
 473         0x40010080,
 474         0x08102040,
 475         0x0,
 476         0x0,
 477         0x0,
 478         0x0,
 479         0x0
 480 };
 481
 482 const u32
 483 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
 484         0x00A400A4,
 485         0x00390039,
 486         0x00320032,
 487         0x00320032,
 488         0x00320032,
 489         0x00440044,
 490         0x00550055,
 491         0x00550055,
 492         0x00550055,
 493         0x00550055,
 494         0x007F007F,
 495         0x004D004D,
 496         0x00430043,
 497         0x00560056,
 498         0x00540054,
 499         0x00600060,
 500         0x0,
 501         0x00600020,
 502         0x40010080,
 503         0x08102040,
 504         0x0,
 505         0x0,
 506         0x0,
 507         0x0,
 508         0x0
 509 };
 510
 511 const struct lpddr2_mr_regs mr_regs = {
 512         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 513         .mr2    = 0x6,
 514         .mr3    = 0x1,
 515         .mr10   = MR10_ZQ_ZQINIT,
 516         .mr16   = MR16_REF_FULL_ARRAY
 517 };
 518
 519 void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 520                                              const u32 **regs,
 521                                              u32 *size)
 522 {
 523         switch (omap_revision()) {
 524         case OMAP5430_ES1_0:
 525         case OMAP5430_ES2_0:
 526                 *regs = ext_phy_ctrl_const_base;
 527                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 528                 break;
 529         case OMAP5432_ES1_0:
 530                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 531                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 532                 break;
 533         case OMAP5432_ES2_0:
 534                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 535                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 536                 break;
 537         case DRA752_ES1_0:
 538         case DRA752_ES1_1:
 539                 if (emif_nr == 1) {
 540                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 541                         *size =
 542                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
 543                 } else {
 544                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 545                         *size =
 546                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
 547                 }
 548                 break;
 549         case DRA722_ES1_0:
 550                 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
 551                 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 552                 break;
 553         default:
 554                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 555                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 556
 557         }
 558 }
 559
 560 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 561 {
 562         *regs = &mr_regs;
 563 }
 564
 565 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 566 {
 567         u32 *ext_phy_ctrl_base = 0;
 568         u32 *emif_ext_phy_ctrl_base = 0;
 569         u32 emif_nr;
 570         const u32 *ext_phy_ctrl_const_regs;
 571         u32 i = 0;
 572         u32 size;
 573
 574         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 575
 576         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 577
 578         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 579         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 580
 581         /* Configure external phy control timing registers */
 582         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 583                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 584                 /* Update shadow registers */
 585                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 586         }
 587
 588         /*
 589          * external phy 6-24 registers do not change with
 590          * ddr frequency
 591          */
 592         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 593                                          &ext_phy_ctrl_const_regs, &size);
 594
 595         for (i = 0; i < size; i++) {
 596                 writel(ext_phy_ctrl_const_regs[i],
 597                        emif_ext_phy_ctrl_base++);
 598                 /* Update shadow registers */
 599                 writel(ext_phy_ctrl_const_regs[i],
 600                        emif_ext_phy_ctrl_base++);
 601         }
 602 }
 603
 604 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 605 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 606         .max_freq       = 532000000,
 607         .RL             = 8,
 608         .tRPab          = 21,
 609         .tRCD           = 18,
 610         .tWR            = 15,
 611         .tRASmin        = 42,
 612         .tRRD           = 10,
 613         .tWTRx2         = 15,
 614         .tXSR           = 140,
 615         .tXPx2          = 15,
 616         .tRFCab         = 130,
 617         .tRTPx2         = 15,
 618         .tCKE           = 3,
 619         .tCKESR         = 15,
 620         .tZQCS          = 90,
 621         .tZQCL          = 360,
 622         .tZQINIT        = 1000,
 623         .tDQSCKMAXx2    = 11,
 624         .tRASmax        = 70,
 625         .tFAW           = 50
 626 };
 627
 628 static const struct lpddr2_min_tck min_tck = {
 629         .tRL            = 3,
 630         .tRP_AB         = 3,
 631         .tRCD           = 3,
 632         .tWR            = 3,
 633         .tRAS_MIN       = 3,
 634         .tRRD           = 2,
 635         .tWTR           = 2,
 636         .tXP            = 2,
 637         .tRTP           = 2,
 638         .tCKE           = 3,
 639         .tCKESR         = 3,
 640         .tFAW           = 8
 641 };
 642
 643 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 644         &timings_jedec_532_mhz
 645 };
 646
 647 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 648         .ac_timings     = ac_timings,
 649         .min_tck        = &min_tck,
 650 };
 651
 652 /*
 653  * List of status registers to be controlled back to control registers
 654  * after initial leveling
 655  * readreg, writereg
 656  */
 657 const struct read_write_regs omap5_bug_00339_regs[] = {
 658         { 8,  5 },
 659         { 9,  6 },
 660         { 10, 7 },
 661         { 14, 8 },
 662         { 15, 9 },
 663         { 16, 10 },
 664         { 11, 2 },
 665         { 12, 3 },
 666         { 13, 4 },
 667         { 17, 11 },
 668         { 18, 12 },
 669         { 19, 13 },
 670 };
 671
 672 const struct read_write_regs dra_bug_00339_regs[] = {
 673         { 7,  7 },
 674         { 8,  8 },
 675         { 9,  9 },
 676         { 10, 10 },
 677         { 11, 11 },
 678         { 12, 2 },
 679         { 13, 3 },
 680         { 14, 4 },
 681         { 15, 5 },
 682         { 16, 6 },
 683         { 17, 12 },
 684         { 18, 13 },
 685         { 19, 14 },
 686         { 20, 15 },
 687         { 21, 16 },
 688         { 22, 17 },
 689         { 23, 18 },
 690         { 24, 19 },
 691         { 25, 20 },
 692         { 26, 21}
 693 };
 694
 695 const struct read_write_regs *get_bug_regs(u32 *iterations)
 696 {
 697         const struct read_write_regs *bug_00339_regs_ptr = NULL;
 698
 699         switch (omap_revision()) {
 700         case OMAP5430_ES1_0:
 701         case OMAP5430_ES2_0:
 702         case OMAP5432_ES1_0:
 703         case OMAP5432_ES2_0:
 704                 bug_00339_regs_ptr = omap5_bug_00339_regs;
 705                 *iterations = sizeof(omap5_bug_00339_regs)/
 706                              sizeof(omap5_bug_00339_regs[0]);
 707                 break;
 708         case DRA752_ES1_0:
 709         case DRA752_ES1_1:
 710         case DRA722_ES1_0:
 711                 bug_00339_regs_ptr = dra_bug_00339_regs;
 712                 *iterations = sizeof(dra_bug_00339_regs)/
 713                              sizeof(dra_bug_00339_regs[0]);
 714                 break;
 715         default:
 716                 printf("\n Error: UnKnown SOC");
 717         }
 718
 719         return bug_00339_regs_ptr;
 720 }
 721
 722 void emif_get_device_timings_sdp(u32 emif_nr,
 723                 const struct lpddr2_device_timings **cs0_device_timings,
 724                 const struct lpddr2_device_timings **cs1_device_timings)
 725 {
 726         /* Identical devices on EMIF1 & EMIF2 */
 727         *cs0_device_timings = &dev_4G_S4_timings;
 728         *cs1_device_timings = &dev_4G_S4_timings;
 729 }
 730
 731 void emif_get_device_timings(u32 emif_nr,
 732                 const struct lpddr2_device_timings **cs0_device_timings,
 733                 const struct lpddr2_device_timings **cs1_device_timings)
 734         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 735
 736 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */