2 * Timing and Organization details of the ddr device parts used in OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
9 * Sricharan R <r.sricharan@ti.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/sys_proto.h>
34 * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
35 * EVM. Since the parts used and geometry are identical for
36 * evm for a given OMAP5 revision, this information is kept
37 * here instead of being in board directory. However the key functions
38 * exported are weakly linked so that they can be over-ridden in the board
39 * directory if there is a OMAP5 board in the future that uses a different
40 * memory device or geometry.
42 * For any new board with different memory devices over-ride one or more
43 * of the following functions as per the CONFIG flags you intend to enable:
44 * - emif_get_reg_dump()
45 * - emif_get_dmm_regs()
46 * - emif_get_device_details()
47 * - emif_get_device_timings()
50 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
51 const struct emif_regs emif_regs_532_mhz_2cs = {
52 .sdram_config_init = 0x80800EBA,
53 .sdram_config = 0x808022BA,
54 .ref_ctrl = 0x0000081A,
55 .sdram_tim1 = 0x772F6873,
56 .sdram_tim2 = 0x304a129a,
57 .sdram_tim3 = 0x02f7e45f,
58 .read_idle_ctrl = 0x00050000,
59 .zq_config = 0x000b3215,
60 .temp_alert_config = 0x08000a05,
61 .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
62 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
63 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
64 .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
65 .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
66 .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
67 .emif_ddr_ext_phy_ctrl_5 = 0x04010040
70 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
71 .sdram_config_init = 0x80800EBA,
72 .sdram_config = 0x808022BA,
73 .ref_ctrl = 0x0000081A,
74 .sdram_tim1 = 0x772F6873,
75 .sdram_tim2 = 0x304a129a,
76 .sdram_tim3 = 0x02f7e45f,
77 .read_idle_ctrl = 0x00050000,
78 .zq_config = 0x100b3215,
79 .temp_alert_config = 0x08000a05,
80 .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
81 .emif_ddr_phy_ctlr_1 = 0x0E30400d,
82 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
83 .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
84 .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
85 .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
86 .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
89 const struct emif_regs emif_regs_266_mhz_2cs = {
90 .sdram_config_init = 0x80800EBA,
91 .sdram_config = 0x808022BA,
92 .ref_ctrl = 0x0000040D,
93 .sdram_tim1 = 0x2A86B419,
94 .sdram_tim2 = 0x1025094A,
95 .sdram_tim3 = 0x026BA22F,
96 .read_idle_ctrl = 0x00050000,
97 .zq_config = 0x000b3215,
98 .temp_alert_config = 0x08000a05,
99 .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
100 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
101 .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
102 .emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
103 .emif_ddr_ext_phy_ctrl_3 = 0x14829052,
104 .emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
105 .emif_ddr_ext_phy_ctrl_5 = 0x04010040
108 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
109 .sdram_config_init = 0x61851B32,
110 .sdram_config = 0x61851B32,
111 .ref_ctrl = 0x00001035,
112 .sdram_tim1 = 0xCCCF36B3,
113 .sdram_tim2 = 0x308F7FDA,
114 .sdram_tim3 = 0x027F88A8,
115 .read_idle_ctrl = 0x00050000,
116 .zq_config = 0x0007190B,
117 .temp_alert_config = 0x00000000,
118 .emif_ddr_phy_ctlr_1_init = 0x0020420A,
119 .emif_ddr_phy_ctlr_1 = 0x0024420A,
120 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
121 .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
122 .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
123 .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
124 .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
125 .emif_rd_wr_lvl_rmp_win = 0x00000000,
126 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
127 .emif_rd_wr_lvl_ctl = 0x00000000,
128 .emif_rd_wr_exec_thresh = 0x00000305
131 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
132 .sdram_config_init = 0x61851B32,
133 .sdram_config = 0x61851B32,
134 .ref_ctrl = 0x00001035,
135 .sdram_tim1 = 0xCCCF36B3,
136 .sdram_tim2 = 0x308F7FDA,
137 .sdram_tim3 = 0x027F88A8,
138 .read_idle_ctrl = 0x00050000,
139 .zq_config = 0x1007190B,
140 .temp_alert_config = 0x00000000,
141 .emif_ddr_phy_ctlr_1_init = 0x0030400A,
142 .emif_ddr_phy_ctlr_1 = 0x0034400A,
143 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
144 .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
145 .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
146 .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
147 .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
148 .emif_rd_wr_lvl_rmp_win = 0x00000000,
149 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
150 .emif_rd_wr_lvl_ctl = 0x00000000,
151 .emif_rd_wr_exec_thresh = 0x40000305
154 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
155 .dmm_lisa_map_0 = 0x0,
156 .dmm_lisa_map_1 = 0x0,
157 .dmm_lisa_map_2 = 0x80740300,
158 .dmm_lisa_map_3 = 0xFF020100
161 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
163 switch (omap_revision()) {
165 *regs = &emif_regs_532_mhz_2cs;
168 *regs = &emif_regs_ddr3_532_mhz_1cs;
171 *regs = &emif_regs_532_mhz_2cs_es2;
175 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
179 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
180 __attribute__((weak, alias("emif_get_reg_dump_sdp")));
182 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
185 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
188 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
189 __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
192 static const struct lpddr2_device_details dev_4G_S4_details = {
193 .type = LPDDR2_TYPE_S4,
194 .density = LPDDR2_DENSITY_4Gb,
195 .io_width = LPDDR2_IO_WIDTH_32,
196 .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
199 static void emif_get_device_details_sdp(u32 emif_nr,
200 struct lpddr2_device_details *cs0_device_details,
201 struct lpddr2_device_details *cs1_device_details)
203 /* EMIF1 & EMIF2 have identical configuration */
204 *cs0_device_details = dev_4G_S4_details;
205 *cs1_device_details = dev_4G_S4_details;
208 void emif_get_device_details(u32 emif_nr,
209 struct lpddr2_device_details *cs0_device_details,
210 struct lpddr2_device_details *cs1_device_details)
211 __attribute__((weak, alias("emif_get_device_details_sdp")));
213 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
215 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
237 const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
259 const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
281 const struct lpddr2_mr_regs mr_regs = {
282 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
285 .mr10 = MR10_ZQ_ZQINIT,
286 .mr16 = MR16_REF_FULL_ARRAY
289 static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
291 switch (omap_revision()) {
294 *regs = ext_phy_ctrl_const_base;
297 *regs = ddr3_ext_phy_ctrl_const_base_es1;
301 *regs = ddr3_ext_phy_ctrl_const_base_es2;
306 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
311 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
313 u32 *ext_phy_ctrl_base = 0;
314 u32 *emif_ext_phy_ctrl_base = 0;
315 const u32 *ext_phy_ctrl_const_regs;
318 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
320 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
321 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
323 /* Configure external phy control timing registers */
324 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
325 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
326 /* Update shadow registers */
327 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
331 * external phy 6-24 registers do not change with
334 emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
335 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
336 writel(ext_phy_ctrl_const_regs[i],
337 emif_ext_phy_ctrl_base++);
338 /* Update shadow registers */
339 writel(ext_phy_ctrl_const_regs[i],
340 emif_ext_phy_ctrl_base++);
344 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
345 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
346 .max_freq = 532000000,
368 static const struct lpddr2_min_tck min_tck = {
383 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
384 &timings_jedec_532_mhz
387 static const struct lpddr2_device_timings dev_4G_S4_timings = {
388 .ac_timings = ac_timings,
392 void emif_get_device_timings_sdp(u32 emif_nr,
393 const struct lpddr2_device_timings **cs0_device_timings,
394 const struct lpddr2_device_timings **cs1_device_timings)
396 /* Identical devices on EMIF1 & EMIF2 */
397 *cs0_device_timings = &dev_4G_S4_timings;
398 *cs1_device_timings = &dev_4G_S4_timings;
401 void emif_get_device_timings(u32 emif_nr,
402 const struct lpddr2_device_timings **cs0_device_timings,
403 const struct lpddr2_device_timings **cs1_device_timings)
404 __attribute__((weak, alias("emif_get_device_timings_sdp")));
406 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */