arch/arm/cpu/armv7/omap5/hwinit.c

   1 /*
   2  *
   3  * Functions for omap5 based boards.
   4  *
   5  * (C) Copyright 2011
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *      Sricharan       <r.sricharan@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31 #include <common.h>
  32 #include <asm/armv7.h>
  33 #include <asm/arch/cpu.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <asm/sizes.h>
  36 #include <asm/utils.h>
  37 #include <asm/arch/gpio.h>
  38 #include <asm/emif.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
  43
  44 static struct gpio_bank gpio_bank_54xx[6] = {
  45         { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
  46         { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
  47         { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
  48         { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
  49         { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
  50         { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
  51 };
  52
  53 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  54
  55 #ifdef CONFIG_SPL_BUILD
  56 /* LPDDR2 specific IO settings */
  57 static void io_settings_lpddr2(void)
  58 {
  59         struct omap_sys_ctrl_regs *ioregs_base =
  60                       (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  61
  62         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  63                                 &(ioregs_base->control_ddrch1_0));
  64         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  65                                 &(ioregs_base->control_ddrch1_1));
  66         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  67                                 &(ioregs_base->control_ddrch2_0));
  68         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  69                                 &(ioregs_base->control_ddrch2_1));
  70         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
  71                                 &(ioregs_base->control_lpddr2ch1_0));
  72         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
  73                                 &(ioregs_base->control_lpddr2ch1_1));
  74         writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
  75                                 &(ioregs_base->control_ddrio_0));
  76         writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
  77                                 &(ioregs_base->control_ddrio_1));
  78         writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
  79                                 &(ioregs_base->control_ddrio_2));
  80 }
  81
  82 /* DDR3 specific IO settings */
  83 static void io_settings_ddr3(void)
  84 {
  85         u32 io_settings = 0;
  86         struct omap_sys_ctrl_regs *ioregs_base =
  87                       (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  88
  89         writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
  90                                 &(ioregs_base->control_ddr3ch1_0));
  91         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  92                                 &(ioregs_base->control_ddrch1_0));
  93         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  94                                 &(ioregs_base->control_ddrch1_1));
  95
  96         writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
  97                                 &(ioregs_base->control_ddr3ch2_0));
  98         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  99                                 &(ioregs_base->control_ddrch2_0));
 100         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
 101                                 &(ioregs_base->control_ddrch2_1));
 102
 103         writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
 104                                 &(ioregs_base->control_ddrio_0));
 105         writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 106                                 &(ioregs_base->control_ddrio_1));
 107         writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 108                                 &(ioregs_base->control_ddrio_2));
 109
 110         /* omap5432 does not use lpddr2 */
 111         writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
 112         writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
 113
 114         writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 115                         &(ioregs_base->control_emif1_sdram_config_ext));
 116         writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 117                         &(ioregs_base->control_emif2_sdram_config_ext));
 118
 119         /* Disable DLL select */
 120         io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
 121                                                         & 0xFFEFFFFF);
 122         writel(io_settings,
 123                 &(ioregs_base->control_port_emif1_sdram_config));
 124
 125         io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
 126                                                         & 0xFFEFFFFF);
 127         writel(io_settings,
 128                 &(ioregs_base->control_port_emif2_sdram_config));
 129 }
 130
 131 /*
 132  * Some tuning of IOs for optimal power and performance
 133  */
 134 void do_io_settings(void)
 135 {
 136         u32 io_settings = 0, mask = 0;
 137         struct omap_sys_ctrl_regs *ioregs_base =
 138                       (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 139
 140         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 141         mask = (ds_mask << 2) | (ds_mask << 8) |
 142                 (ds_mask << 16) | (ds_mask << 18);
 143         io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
 144                                 (~mask);
 145         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 146                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 147         writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
 148
 149         /* Impedance settings Mcspi2 */
 150         mask = (ds_mask << 30);
 151         io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
 152                         (~mask);
 153         io_settings |= (ds_60_ohm << 30);
 154         writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
 155
 156         /* Impedance settings C2C 3,4 */
 157         mask = (ds_mask << 14) | (ds_mask << 16);
 158         io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
 159                         (~mask);
 160         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 161         writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
 162
 163         /* Slew rate settings EMMC, C2C 1,2 */
 164         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 165         io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
 166                         (~mask);
 167         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 168         writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
 169
 170         /* Slew rate settings hsi2, Mcspi2 */
 171         mask = (sc_mask << 24) | (sc_mask << 28);
 172         io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
 173                         (~mask);
 174         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 175         writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
 176
 177         /* Slew rate settings C2C 3,4 */
 178         mask = (sc_mask << 16) | (sc_mask << 18);
 179         io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
 180                         (~mask);
 181         io_settings |= (sc_na << 16) | (sc_na << 18);
 182         writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
 183
 184         /* impedance and slew rate settings for usb */
 185         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 186                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 187         io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
 188                         (~mask);
 189         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 190                        (ds_60_ohm << 23) | (sc_fast << 20) |
 191                        (sc_fast << 17) | (sc_fast << 14);
 192         writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
 193
 194         if (omap_revision() <= OMAP5430_ES1_0)
 195                 io_settings_lpddr2();
 196         else
 197                 io_settings_ddr3();
 198
 199         /* Efuse settings */
 200         writel(EFUSE_1, &(ioregs_base->control_efuse_1));
 201         writel(EFUSE_2, &(ioregs_base->control_efuse_2));
 202         writel(EFUSE_3, &(ioregs_base->control_efuse_3));
 203         writel(EFUSE_4, &(ioregs_base->control_efuse_4));
 204 }
 205 #endif
 206
 207 void config_data_eye_leveling_samples(u32 emif_base)
 208 {
 209         struct omap_sys_ctrl_regs *ioregs_base =
 210                 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 211
 212         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 213         if (emif_base == EMIF1_BASE)
 214                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 215                         &(ioregs_base->control_emif1_sdram_config_ext));
 216         else if (emif_base == EMIF2_BASE)
 217                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 218                         &(ioregs_base->control_emif2_sdram_config_ext));
 219 }
 220
 221 void init_omap_revision(void)
 222 {
 223         /*
 224          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 225          * Also, ES1 and ES2 have different ARM revisions
 226          * So use ARM revision for identification
 227          */
 228         unsigned int rev = cortex_rev();
 229
 230         switch (rev) {
 231         case MIDR_CORTEX_A15_R0P0:
 232                 switch (readl(CONTROL_ID_CODE)) {
 233                 case OMAP5430_CONTROL_ID_CODE_ES1_0:
 234                         *omap_si_rev = OMAP5430_ES1_0;
 235                         break;
 236                 case OMAP5432_CONTROL_ID_CODE_ES1_0:
 237                 default:
 238                         *omap_si_rev = OMAP5432_ES1_0;
 239                         break;
 240                 }
 241                 break;
 242         default:
 243                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 244         }
 245 }
 246
 247 void reset_cpu(ulong ignored)
 248 {
 249         u32 omap_rev = omap_revision();
 250
 251         /*
 252          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 253          * So use cold reset in case instead.
 254          */
 255         if (omap_rev == OMAP5430_ES1_0)
 256                 writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
 257         else
 258                 writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
 259 }