arch/arm/cpu/armv7/omap5/hwinit.c

   1 /*
   2  *
   3  * Functions for omap5 based boards.
   4  *
   5  * (C) Copyright 2011
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *      Sricharan       <r.sricharan@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15 #include <common.h>
  16 #include <asm/armv7.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/sizes.h>
  21 #include <asm/utils.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/emif.h>
  24 #include <asm/omap_common.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  29
  30 static struct gpio_bank gpio_bank_54xx[8] = {
  31         { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
  32         { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
  33         { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
  34         { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
  35         { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
  36         { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
  37         { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
  38         { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
  39 };
  40
  41 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  42
  43 #ifdef CONFIG_SPL_BUILD
  44 /* LPDDR2 specific IO settings */
  45 static void io_settings_lpddr2(void)
  46 {
  47         const struct ctrl_ioregs *ioregs;
  48
  49         get_ioregs(&ioregs);
  50         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  51         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  52         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  53         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  54         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  55         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  56         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  57         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  58         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  59 }
  60
  61 /* DDR3 specific IO settings */
  62 static void io_settings_ddr3(void)
  63 {
  64         u32 io_settings = 0;
  65         const struct ctrl_ioregs *ioregs;
  66
  67         get_ioregs(&ioregs);
  68         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  69         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  70         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  71
  72         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  73         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  74         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  75
  76         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  77         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  78         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  79
  80         /* omap5432 does not use lpddr2 */
  81         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  82         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  83
  84         writel(ioregs->ctrl_emif_sdram_config_ext,
  85                (*ctrl)->control_emif1_sdram_config_ext);
  86         writel(ioregs->ctrl_emif_sdram_config_ext,
  87                (*ctrl)->control_emif2_sdram_config_ext);
  88
  89         if (is_omap54xx()) {
  90                 /* Disable DLL select */
  91                 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
  92                                                         & 0xFFEFFFFF);
  93                 writel(io_settings,
  94                         (*ctrl)->control_port_emif1_sdram_config);
  95
  96                 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
  97                                                         & 0xFFEFFFFF);
  98                 writel(io_settings,
  99                         (*ctrl)->control_port_emif2_sdram_config);
 100         } else {
 101                 writel(ioregs->ctrl_ddr_ctrl_ext_0,
 102                                 (*ctrl)->control_ddr_control_ext_0);
 103         }
 104 }
 105
 106 /*
 107  * Some tuning of IOs for optimal power and performance
 108  */
 109 void do_io_settings(void)
 110 {
 111         u32 io_settings = 0, mask = 0;
 112
 113         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 114         mask = (ds_mask << 2) | (ds_mask << 8) |
 115                 (ds_mask << 16) | (ds_mask << 18);
 116         io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 117                                 (~mask);
 118         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 119                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 120         writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 121
 122         /* Impedance settings Mcspi2 */
 123         mask = (ds_mask << 30);
 124         io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 125                         (~mask);
 126         io_settings |= (ds_60_ohm << 30);
 127         writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 128
 129         /* Impedance settings C2C 3,4 */
 130         mask = (ds_mask << 14) | (ds_mask << 16);
 131         io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 132                         (~mask);
 133         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 134         writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 135
 136         /* Slew rate settings EMMC, C2C 1,2 */
 137         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 138         io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 139                         (~mask);
 140         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 141         writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 142
 143         /* Slew rate settings hsi2, Mcspi2 */
 144         mask = (sc_mask << 24) | (sc_mask << 28);
 145         io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 146                         (~mask);
 147         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 148         writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 149
 150         /* Slew rate settings C2C 3,4 */
 151         mask = (sc_mask << 16) | (sc_mask << 18);
 152         io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 153                         (~mask);
 154         io_settings |= (sc_na << 16) | (sc_na << 18);
 155         writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 156
 157         /* impedance and slew rate settings for usb */
 158         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 159                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 160         io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 161                         (~mask);
 162         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 163                        (ds_60_ohm << 23) | (sc_fast << 20) |
 164                        (sc_fast << 17) | (sc_fast << 14);
 165         writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 166
 167         if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 168                 io_settings_lpddr2();
 169         else
 170                 io_settings_ddr3();
 171
 172         /* Efuse settings */
 173         writel(EFUSE_1, (*ctrl)->control_efuse_1);
 174         writel(EFUSE_2, (*ctrl)->control_efuse_2);
 175         writel(EFUSE_3, (*ctrl)->control_efuse_3);
 176         writel(EFUSE_4, (*ctrl)->control_efuse_4);
 177 }
 178
 179 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 180         {0x45, 0x1},    /* 12 MHz   */
 181         {-1, -1},       /* 13 MHz   */
 182         {0x63, 0x2},    /* 16.8 MHz */
 183         {0x57, 0x2},    /* 19.2 MHz */
 184         {0x20, 0x1},    /* 26 MHz   */
 185         {-1, -1},       /* 27 MHz   */
 186         {0x41, 0x3}     /* 38.4 MHz */
 187 };
 188
 189 void srcomp_enable(void)
 190 {
 191         u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 192         u32 sysclk_ind  = get_sys_clk_index();
 193         u32 omap_rev    = omap_revision();
 194
 195         if (!is_omap54xx())
 196                 return;
 197
 198         mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 199         div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 200
 201         for (i = 0; i < 4; i++) {
 202                 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 203                 srcomp_value &=
 204                         ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 205                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 206                         (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 207                 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 208         }
 209
 210         if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 211                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 212                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 213                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 214
 215                 for (i = 0; i < 4; i++) {
 216                         srcomp_value =
 217                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 218                         srcomp_value &= ~PWRDWN_XS_MASK;
 219                         writel(srcomp_value,
 220                                (*ctrl)->control_srcomp_north_side + i*4);
 221
 222                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 223                                 & SRCODE_READ_XS_MASK) >>
 224                                 SRCODE_READ_XS_SHIFT) == 0)
 225                                 ;
 226
 227                         srcomp_value =
 228                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 229                         srcomp_value &= ~OVERRIDE_XS_MASK;
 230                         writel(srcomp_value,
 231                                (*ctrl)->control_srcomp_north_side + i*4);
 232                 }
 233         } else {
 234                 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 235                 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 236                                   DIVIDE_FACTOR_XS_MASK);
 237                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 238                                 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 239                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 240
 241                 for (i = 0; i < 4; i++) {
 242                         srcomp_value =
 243                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 244                         srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 245                         writel(srcomp_value,
 246                                (*ctrl)->control_srcomp_north_side + i*4);
 247
 248                         srcomp_value =
 249                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 250                         srcomp_value &= ~OVERRIDE_XS_MASK;
 251                         writel(srcomp_value,
 252                                (*ctrl)->control_srcomp_north_side + i*4);
 253                 }
 254
 255                 srcomp_value =
 256                         readl((*ctrl)->control_srcomp_east_side_wkup);
 257                 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 258                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 259
 260                 srcomp_value =
 261                         readl((*ctrl)->control_srcomp_east_side_wkup);
 262                 srcomp_value &= ~OVERRIDE_XS_MASK;
 263                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 264
 265                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 266                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 267                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 268
 269                 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 270                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 271                 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 272
 273                 for (i = 0; i < 4; i++) {
 274                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 275                                 & SRCODE_READ_XS_MASK) >>
 276                                 SRCODE_READ_XS_SHIFT) == 0)
 277                                 ;
 278
 279                         srcomp_value =
 280                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 281                         srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 282                         writel(srcomp_value,
 283                                (*ctrl)->control_srcomp_north_side + i*4);
 284                 }
 285
 286                 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 287                         SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 288                         ;
 289
 290                 srcomp_value =
 291                         readl((*ctrl)->control_srcomp_east_side_wkup);
 292                 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 293                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 294         }
 295 }
 296 #endif
 297
 298 void config_data_eye_leveling_samples(u32 emif_base)
 299 {
 300         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 301         if (emif_base == EMIF1_BASE)
 302                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 303                         (*ctrl)->control_emif1_sdram_config_ext);
 304         else if (emif_base == EMIF2_BASE)
 305                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 306                         (*ctrl)->control_emif2_sdram_config_ext);
 307 }
 308
 309 void init_omap_revision(void)
 310 {
 311         /*
 312          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 313          * Also, ES1 and ES2 have different ARM revisions
 314          * So use ARM revision for identification
 315          */
 316         unsigned int rev = cortex_rev();
 317
 318         switch (readl(CONTROL_ID_CODE)) {
 319         case OMAP5430_CONTROL_ID_CODE_ES1_0:
 320                 *omap_si_rev = OMAP5430_ES1_0;
 321                 if (rev == MIDR_CORTEX_A15_R2P2)
 322                         *omap_si_rev = OMAP5430_ES2_0;
 323                 break;
 324         case OMAP5432_CONTROL_ID_CODE_ES1_0:
 325                 *omap_si_rev = OMAP5432_ES1_0;
 326                 if (rev == MIDR_CORTEX_A15_R2P2)
 327                         *omap_si_rev = OMAP5432_ES2_0;
 328                 break;
 329         case OMAP5430_CONTROL_ID_CODE_ES2_0:
 330                 *omap_si_rev = OMAP5430_ES2_0;
 331                 break;
 332         case OMAP5432_CONTROL_ID_CODE_ES2_0:
 333                 *omap_si_rev = OMAP5432_ES2_0;
 334                 break;
 335         case DRA752_CONTROL_ID_CODE_ES1_0:
 336                 *omap_si_rev = DRA752_ES1_0;
 337                 break;
 338         default:
 339                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 340         }
 341 }
 342
 343 void reset_cpu(ulong ignored)
 344 {
 345         u32 omap_rev = omap_revision();
 346
 347         /*
 348          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 349          * So use cold reset in case instead.
 350          */
 351         if (omap_rev == OMAP5430_ES1_0)
 352                 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 353         else
 354                 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 355 }
 356
 357 u32 warm_reset(void)
 358 {
 359         return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 360 }
 361
 362 void setup_warmreset_time(void)
 363 {
 364         u32 rst_time, rst_val;
 365
 366 #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
 367         rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
 368 #else
 369         rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
 370 #endif
 371         rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
 372
 373         if (rst_time > RSTTIME1_MASK)
 374                 rst_time = RSTTIME1_MASK;
 375
 376         rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 377         rst_val |= rst_time;
 378         writel(rst_val, (*prcm)->prm_rsttime);
 379 }