3 * HW data initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/omap.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/clock.h>
17 #include <asm/omap_gpio.h>
20 struct prcm_regs const **prcm =
21 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
22 struct dplls const **dplls_data =
23 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
24 struct vcores_data const **omap_vcores =
25 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
26 struct omap_sys_ctrl_regs const **ctrl =
27 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
30 * The M & N values in the following tables are created using the
32 * tools/omap/clocks_get_m_n.c
33 * Please use this tool for creating the table for any new frequency.
37 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
38 * OMAP4460 OPP_NOM frequency
40 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
41 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
42 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
43 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
44 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
45 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
46 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
47 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
51 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
52 * OMAP4430 OPP_TURBO frequency
54 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
65 * dpll locked at 1200 MHz - MPU clk at 600 MHz
66 * OMAP4430 OPP_NOM frequency
68 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
69 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
70 {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
71 {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
72 {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
73 {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
74 {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
75 {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
78 /* OMAP4460 OPP_NOM frequency */
79 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
80 {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
81 {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
82 {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
83 {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
84 {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
85 {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
86 {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
89 /* OMAP4430 ES1 OPP_NOM frequency */
90 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
91 {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
92 {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
93 {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
94 {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
95 {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
96 {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
97 {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
100 /* OMAP4430 ES2.X OPP_NOM frequency */
101 static const struct dpll_params
102 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
103 {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
104 {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
105 {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
106 {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
107 {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
108 {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
109 {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
112 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
113 {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
114 {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
115 {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
116 {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
117 {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
118 {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
119 {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
122 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
123 {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
124 {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
125 {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
126 {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
127 {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
128 {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
129 {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
132 /* ABE M & N values with sys_clk as source */
133 static const struct dpll_params
134 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
135 {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
136 {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
137 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
138 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
139 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
140 {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
141 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
144 /* ABE M & N values with 32K clock as source */
145 static const struct dpll_params abe_dpll_params_32k_196608khz = {
146 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
149 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
150 {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
151 {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
152 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
153 {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
154 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
155 {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
156 {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
159 struct dplls omap4430_dplls_es1 = {
160 .mpu = mpu_dpll_params_1200mhz,
161 .core = core_dpll_params_es1_1524mhz,
162 .per = per_dpll_params_1536mhz,
163 .iva = iva_dpll_params_1862mhz,
164 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
165 .abe = abe_dpll_params_sysclk_196608khz,
167 .abe = &abe_dpll_params_32k_196608khz,
169 .usb = usb_dpll_params_1920mhz,
173 struct dplls omap4430_dplls = {
174 .mpu = mpu_dpll_params_1200mhz,
175 .core = core_dpll_params_1600mhz,
176 .per = per_dpll_params_1536mhz,
177 .iva = iva_dpll_params_1862mhz,
178 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
179 .abe = abe_dpll_params_sysclk_196608khz,
181 .abe = &abe_dpll_params_32k_196608khz,
183 .usb = usb_dpll_params_1920mhz,
187 struct dplls omap4460_dplls = {
188 .mpu = mpu_dpll_params_1400mhz,
189 .core = core_dpll_params_1600mhz,
190 .per = per_dpll_params_1536mhz,
191 .iva = iva_dpll_params_1862mhz,
192 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
193 .abe = abe_dpll_params_sysclk_196608khz,
195 .abe = &abe_dpll_params_32k_196608khz,
197 .usb = usb_dpll_params_1920mhz,
201 struct pmic_data twl6030_4430es1 = {
202 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
203 .step = 12660, /* 12.66 mV represented in uV */
204 /* The code starts at 1 not 0 */
206 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
207 .pmic_bus_init = sri2c_init,
208 .pmic_write = omap_vc_bypass_send_value,
211 struct pmic_data twl6030 = {
212 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
213 .step = 12660, /* 12.66 mV represented in uV */
214 /* The code starts at 1 not 0 */
216 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
217 .pmic_bus_init = sri2c_init,
218 .pmic_write = omap_vc_bypass_send_value,
221 struct pmic_data tps62361 = {
222 .base_offset = TPS62361_BASE_VOLT_MV,
223 .step = 10000, /* 10 mV represented in uV */
225 .gpio = TPS62361_VSEL0_GPIO,
227 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
228 .pmic_bus_init = sri2c_init,
229 .pmic_write = omap_vc_bypass_send_value,
232 struct vcores_data omap4430_volts_es1 = {
234 .mpu.addr = SMPS_REG_ADDR_VCORE1,
235 .mpu.pmic = &twl6030_4430es1,
238 .core.addr = SMPS_REG_ADDR_VCORE3,
239 .core.pmic = &twl6030_4430es1,
242 .mm.addr = SMPS_REG_ADDR_VCORE2,
243 .mm.pmic = &twl6030_4430es1,
246 struct vcores_data omap4430_volts = {
248 .mpu.addr = SMPS_REG_ADDR_VCORE1,
249 .mpu.pmic = &twl6030,
252 .core.addr = SMPS_REG_ADDR_VCORE3,
253 .core.pmic = &twl6030,
256 .mm.addr = SMPS_REG_ADDR_VCORE2,
260 struct vcores_data omap4460_volts = {
262 .mpu.addr = TPS62361_REG_ADDR_SET1,
263 .mpu.pmic = &tps62361,
266 .core.addr = SMPS_REG_ADDR_VCORE1,
267 .core.pmic = &twl6030,
270 .mm.addr = SMPS_REG_ADDR_VCORE2,
275 * Enable essential clock domains, modules and
276 * do some additional special settings needed
278 void enable_basic_clocks(void)
280 u32 const clk_domains_essential[] = {
281 (*prcm)->cm_l4per_clkstctrl,
282 (*prcm)->cm_l3init_clkstctrl,
283 (*prcm)->cm_memif_clkstctrl,
284 (*prcm)->cm_l4cfg_clkstctrl,
288 u32 const clk_modules_hw_auto_essential[] = {
289 (*prcm)->cm_l3_gpmc_clkctrl,
290 (*prcm)->cm_memif_emif_1_clkctrl,
291 (*prcm)->cm_memif_emif_2_clkctrl,
292 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
293 (*prcm)->cm_wkup_gpio1_clkctrl,
294 (*prcm)->cm_l4per_gpio2_clkctrl,
295 (*prcm)->cm_l4per_gpio3_clkctrl,
296 (*prcm)->cm_l4per_gpio4_clkctrl,
297 (*prcm)->cm_l4per_gpio5_clkctrl,
298 (*prcm)->cm_l4per_gpio6_clkctrl,
302 u32 const clk_modules_explicit_en_essential[] = {
303 (*prcm)->cm_wkup_gptimer1_clkctrl,
304 (*prcm)->cm_l3init_hsmmc1_clkctrl,
305 (*prcm)->cm_l3init_hsmmc2_clkctrl,
306 (*prcm)->cm_l4per_gptimer2_clkctrl,
307 (*prcm)->cm_wkup_wdtimer2_clkctrl,
308 (*prcm)->cm_l4per_uart3_clkctrl,
312 /* Enable optional additional functional clock for GPIO4 */
313 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
314 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
316 /* Enable 96 MHz clock for MMC1 & MMC2 */
317 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
318 HSMMC_CLKCTRL_CLKSEL_MASK);
319 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
320 HSMMC_CLKCTRL_CLKSEL_MASK);
322 /* Select 32KHz clock as the source of GPTIMER1 */
323 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
324 GPTIMER1_CLKCTRL_CLKSEL_MASK);
326 /* Enable optional 48M functional clock for USB PHY */
327 setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
328 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
330 do_enable_clocks(clk_domains_essential,
331 clk_modules_hw_auto_essential,
332 clk_modules_explicit_en_essential,
336 void enable_basic_uboot_clocks(void)
338 u32 const clk_domains_essential[] = {
342 u32 const clk_modules_hw_auto_essential[] = {
343 (*prcm)->cm_l3init_hsusbotg_clkctrl,
344 (*prcm)->cm_l3init_usbphy_clkctrl,
345 (*prcm)->cm_l3init_usbphy_clkctrl,
346 (*prcm)->cm_clksel_usb_60mhz,
347 (*prcm)->cm_l3init_hsusbtll_clkctrl,
351 u32 const clk_modules_explicit_en_essential[] = {
352 (*prcm)->cm_l4per_mcspi1_clkctrl,
353 (*prcm)->cm_l4per_i2c1_clkctrl,
354 (*prcm)->cm_l4per_i2c2_clkctrl,
355 (*prcm)->cm_l4per_i2c3_clkctrl,
356 (*prcm)->cm_l4per_i2c4_clkctrl,
357 (*prcm)->cm_l3init_hsusbhost_clkctrl,
361 do_enable_clocks(clk_domains_essential,
362 clk_modules_hw_auto_essential,
363 clk_modules_explicit_en_essential,
368 * Enable non-essential clock domains, modules and
369 * do some additional special settings needed
371 void enable_non_essential_clocks(void)
373 u32 const clk_domains_non_essential[] = {
374 (*prcm)->cm_mpu_m3_clkstctrl,
375 (*prcm)->cm_ivahd_clkstctrl,
376 (*prcm)->cm_dsp_clkstctrl,
377 (*prcm)->cm_dss_clkstctrl,
378 (*prcm)->cm_sgx_clkstctrl,
379 (*prcm)->cm1_abe_clkstctrl,
380 (*prcm)->cm_c2c_clkstctrl,
381 (*prcm)->cm_cam_clkstctrl,
382 (*prcm)->cm_dss_clkstctrl,
383 (*prcm)->cm_sdma_clkstctrl,
387 u32 const clk_modules_hw_auto_non_essential[] = {
388 (*prcm)->cm_l3instr_l3_3_clkctrl,
389 (*prcm)->cm_l3instr_l3_instr_clkctrl,
390 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
391 (*prcm)->cm_l3init_hsi_clkctrl,
395 u32 const clk_modules_explicit_en_non_essential[] = {
396 (*prcm)->cm1_abe_aess_clkctrl,
397 (*prcm)->cm1_abe_pdm_clkctrl,
398 (*prcm)->cm1_abe_dmic_clkctrl,
399 (*prcm)->cm1_abe_mcasp_clkctrl,
400 (*prcm)->cm1_abe_mcbsp1_clkctrl,
401 (*prcm)->cm1_abe_mcbsp2_clkctrl,
402 (*prcm)->cm1_abe_mcbsp3_clkctrl,
403 (*prcm)->cm1_abe_slimbus_clkctrl,
404 (*prcm)->cm1_abe_timer5_clkctrl,
405 (*prcm)->cm1_abe_timer6_clkctrl,
406 (*prcm)->cm1_abe_timer7_clkctrl,
407 (*prcm)->cm1_abe_timer8_clkctrl,
408 (*prcm)->cm1_abe_wdt3_clkctrl,
409 (*prcm)->cm_l4per_gptimer9_clkctrl,
410 (*prcm)->cm_l4per_gptimer10_clkctrl,
411 (*prcm)->cm_l4per_gptimer11_clkctrl,
412 (*prcm)->cm_l4per_gptimer3_clkctrl,
413 (*prcm)->cm_l4per_gptimer4_clkctrl,
414 (*prcm)->cm_l4per_hdq1w_clkctrl,
415 (*prcm)->cm_l4per_mcbsp4_clkctrl,
416 (*prcm)->cm_l4per_mcspi2_clkctrl,
417 (*prcm)->cm_l4per_mcspi3_clkctrl,
418 (*prcm)->cm_l4per_mcspi4_clkctrl,
419 (*prcm)->cm_l4per_mmcsd3_clkctrl,
420 (*prcm)->cm_l4per_mmcsd4_clkctrl,
421 (*prcm)->cm_l4per_mmcsd5_clkctrl,
422 (*prcm)->cm_l4per_uart1_clkctrl,
423 (*prcm)->cm_l4per_uart2_clkctrl,
424 (*prcm)->cm_l4per_uart4_clkctrl,
425 (*prcm)->cm_wkup_keyboard_clkctrl,
426 (*prcm)->cm_wkup_wdtimer2_clkctrl,
427 (*prcm)->cm_cam_iss_clkctrl,
428 (*prcm)->cm_cam_fdif_clkctrl,
429 (*prcm)->cm_dss_dss_clkctrl,
430 (*prcm)->cm_sgx_sgx_clkctrl,
434 /* Enable optional functional clock for ISS */
435 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
437 /* Enable all optional functional clocks of DSS */
438 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
440 do_enable_clocks(clk_domains_non_essential,
441 clk_modules_hw_auto_non_essential,
442 clk_modules_explicit_en_non_essential,
445 /* Put camera module in no sleep mode */
446 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
447 MODULE_CLKCTRL_MODULEMODE_MASK,
448 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
449 MODULE_CLKCTRL_MODULEMODE_SHIFT);
452 void hw_data_init(void)
454 u32 omap_rev = omap_revision();
456 (*prcm) = &omap4_prcm;
461 *dplls_data = &omap4430_dplls_es1;
462 *omap_vcores = &omap4430_volts_es1;
469 *dplls_data = &omap4430_dplls;
470 *omap_vcores = &omap4430_volts;
475 *dplls_data = &omap4460_dplls;
476 *omap_vcores = &omap4460_volts;
480 printf("\n INVALID OMAP REVISION ");