3 * HW data initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/omap.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/clock.h>
17 #include <asm/omap_gpio.h>
20 struct prcm_regs const **prcm =
21 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
22 struct dplls const **dplls_data =
23 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
24 struct vcores_data const **omap_vcores =
25 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
26 struct omap_sys_ctrl_regs const **ctrl =
27 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
30 * The M & N values in the following tables are created using the
32 * tools/omap/clocks_get_m_n.c
33 * Please use this tool for creating the table for any new frequency.
37 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
38 * OMAP4460 OPP_NOM frequency
40 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
41 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
42 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
43 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
44 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
45 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
46 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
47 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
51 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
52 * OMAP4430 OPP_TURBO frequency
53 * OMAP4470 OPP_NOM frequency
55 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
56 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
57 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
58 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
59 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
60 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
61 {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
62 {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
66 * dpll locked at 1200 MHz - MPU clk at 600 MHz
67 * OMAP4430 OPP_NOM frequency
69 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
70 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
71 {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
72 {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
73 {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
74 {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
75 {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
76 {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
79 /* OMAP4460 OPP_NOM frequency */
80 /* OMAP4470 OPP_NOM (Low Power) frequency */
81 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
82 {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
83 {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
84 {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
85 {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
86 {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
87 {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
88 {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
91 /* OMAP4430 ES1 OPP_NOM frequency */
92 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
93 {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
94 {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
95 {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
96 {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
97 {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
98 {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
99 {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
102 /* OMAP4430 ES2.X OPP_NOM frequency */
103 static const struct dpll_params
104 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
105 {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
106 {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
107 {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
108 {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
109 {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
110 {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
111 {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
114 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
115 {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
116 {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
117 {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
118 {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
119 {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
120 {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
121 {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
124 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
125 {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
126 {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
127 {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
128 {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
129 {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
130 {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
131 {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
134 /* ABE M & N values with sys_clk as source */
135 static const struct dpll_params
136 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
137 {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
138 {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
139 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
140 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
141 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
142 {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
143 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
146 /* ABE M & N values with 32K clock as source */
147 static const struct dpll_params abe_dpll_params_32k_196608khz = {
148 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
151 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
152 {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
153 {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
155 {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
156 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
157 {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
161 struct dplls omap4430_dplls_es1 = {
162 .mpu = mpu_dpll_params_1200mhz,
163 .core = core_dpll_params_es1_1524mhz,
164 .per = per_dpll_params_1536mhz,
165 .iva = iva_dpll_params_1862mhz,
166 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
167 .abe = abe_dpll_params_sysclk_196608khz,
169 .abe = &abe_dpll_params_32k_196608khz,
171 .usb = usb_dpll_params_1920mhz,
175 struct dplls omap4430_dplls = {
176 .mpu = mpu_dpll_params_1200mhz,
177 .core = core_dpll_params_1600mhz,
178 .per = per_dpll_params_1536mhz,
179 .iva = iva_dpll_params_1862mhz,
180 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
181 .abe = abe_dpll_params_sysclk_196608khz,
183 .abe = &abe_dpll_params_32k_196608khz,
185 .usb = usb_dpll_params_1920mhz,
189 struct dplls omap4460_dplls = {
190 .mpu = mpu_dpll_params_1400mhz,
191 .core = core_dpll_params_1600mhz,
192 .per = per_dpll_params_1536mhz,
193 .iva = iva_dpll_params_1862mhz,
194 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
195 .abe = abe_dpll_params_sysclk_196608khz,
197 .abe = &abe_dpll_params_32k_196608khz,
199 .usb = usb_dpll_params_1920mhz,
203 struct dplls omap4470_dplls = {
204 .mpu = mpu_dpll_params_1600mhz,
205 .core = core_dpll_params_1600mhz,
206 .per = per_dpll_params_1536mhz,
207 .iva = iva_dpll_params_1862mhz,
208 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
209 .abe = abe_dpll_params_sysclk_196608khz,
211 .abe = &abe_dpll_params_32k_196608khz,
213 .usb = usb_dpll_params_1920mhz,
217 struct pmic_data twl6030_4430es1 = {
218 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
219 .step = 12660, /* 12.66 mV represented in uV */
220 /* The code starts at 1 not 0 */
222 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
223 .pmic_bus_init = sri2c_init,
224 .pmic_write = omap_vc_bypass_send_value,
227 /* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
228 struct pmic_data twl6030 = {
229 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
230 .step = 12660, /* 12.66 mV represented in uV */
231 /* The code starts at 1 not 0 */
233 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
234 .pmic_bus_init = sri2c_init,
235 .pmic_write = omap_vc_bypass_send_value,
238 struct pmic_data tps62361 = {
239 .base_offset = TPS62361_BASE_VOLT_MV,
240 .step = 10000, /* 10 mV represented in uV */
242 .gpio = TPS62361_VSEL0_GPIO,
244 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
245 .pmic_bus_init = sri2c_init,
246 .pmic_write = omap_vc_bypass_send_value,
249 struct vcores_data omap4430_volts_es1 = {
251 .mpu.addr = SMPS_REG_ADDR_VCORE1,
252 .mpu.pmic = &twl6030_4430es1,
255 .core.addr = SMPS_REG_ADDR_VCORE3,
256 .core.pmic = &twl6030_4430es1,
259 .mm.addr = SMPS_REG_ADDR_VCORE2,
260 .mm.pmic = &twl6030_4430es1,
263 struct vcores_data omap4430_volts = {
265 .mpu.addr = SMPS_REG_ADDR_VCORE1,
266 .mpu.pmic = &twl6030,
269 .core.addr = SMPS_REG_ADDR_VCORE3,
270 .core.pmic = &twl6030,
273 .mm.addr = SMPS_REG_ADDR_VCORE2,
277 struct vcores_data omap4460_volts = {
279 .mpu.addr = TPS62361_REG_ADDR_SET1,
280 .mpu.pmic = &tps62361,
283 .core.addr = SMPS_REG_ADDR_VCORE1,
284 .core.pmic = &twl6030,
287 .mm.addr = SMPS_REG_ADDR_VCORE2,
292 * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
293 * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
295 struct vcores_data omap4470_volts = {
297 .mpu.addr = SMPS_REG_ADDR_SMPS1,
298 .mpu.pmic = &twl6030,
301 .core.addr = SMPS_REG_ADDR_SMPS2,
302 .core.pmic = &twl6030,
305 .mm.addr = SMPS_REG_ADDR_SMPS5,
310 * Enable essential clock domains, modules and
311 * do some additional special settings needed
313 void enable_basic_clocks(void)
315 u32 const clk_domains_essential[] = {
316 (*prcm)->cm_l4per_clkstctrl,
317 (*prcm)->cm_l3init_clkstctrl,
318 (*prcm)->cm_memif_clkstctrl,
319 (*prcm)->cm_l4cfg_clkstctrl,
323 u32 const clk_modules_hw_auto_essential[] = {
324 (*prcm)->cm_l3_gpmc_clkctrl,
325 (*prcm)->cm_memif_emif_1_clkctrl,
326 (*prcm)->cm_memif_emif_2_clkctrl,
327 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
328 (*prcm)->cm_wkup_gpio1_clkctrl,
329 (*prcm)->cm_l4per_gpio2_clkctrl,
330 (*prcm)->cm_l4per_gpio3_clkctrl,
331 (*prcm)->cm_l4per_gpio4_clkctrl,
332 (*prcm)->cm_l4per_gpio5_clkctrl,
333 (*prcm)->cm_l4per_gpio6_clkctrl,
337 u32 const clk_modules_explicit_en_essential[] = {
338 (*prcm)->cm_wkup_gptimer1_clkctrl,
339 (*prcm)->cm_l3init_hsmmc1_clkctrl,
340 (*prcm)->cm_l3init_hsmmc2_clkctrl,
341 (*prcm)->cm_l4per_gptimer2_clkctrl,
342 (*prcm)->cm_wkup_wdtimer2_clkctrl,
343 (*prcm)->cm_l4per_uart3_clkctrl,
347 /* Enable optional additional functional clock for GPIO4 */
348 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
349 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
351 /* Enable 96 MHz clock for MMC1 & MMC2 */
352 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
353 HSMMC_CLKCTRL_CLKSEL_MASK);
354 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
355 HSMMC_CLKCTRL_CLKSEL_MASK);
357 /* Select 32KHz clock as the source of GPTIMER1 */
358 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
359 GPTIMER1_CLKCTRL_CLKSEL_MASK);
361 /* Enable optional 48M functional clock for USB PHY */
362 setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
363 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
365 do_enable_clocks(clk_domains_essential,
366 clk_modules_hw_auto_essential,
367 clk_modules_explicit_en_essential,
371 void enable_basic_uboot_clocks(void)
373 u32 const clk_domains_essential[] = {
377 u32 const clk_modules_hw_auto_essential[] = {
378 (*prcm)->cm_l3init_hsusbotg_clkctrl,
379 (*prcm)->cm_l3init_usbphy_clkctrl,
380 (*prcm)->cm_l3init_usbphy_clkctrl,
381 (*prcm)->cm_clksel_usb_60mhz,
382 (*prcm)->cm_l3init_hsusbtll_clkctrl,
386 u32 const clk_modules_explicit_en_essential[] = {
387 (*prcm)->cm_l4per_mcspi1_clkctrl,
388 (*prcm)->cm_l4per_i2c1_clkctrl,
389 (*prcm)->cm_l4per_i2c2_clkctrl,
390 (*prcm)->cm_l4per_i2c3_clkctrl,
391 (*prcm)->cm_l4per_i2c4_clkctrl,
392 (*prcm)->cm_l3init_hsusbhost_clkctrl,
396 do_enable_clocks(clk_domains_essential,
397 clk_modules_hw_auto_essential,
398 clk_modules_explicit_en_essential,
403 * Enable non-essential clock domains, modules and
404 * do some additional special settings needed
406 void enable_non_essential_clocks(void)
408 u32 const clk_domains_non_essential[] = {
409 (*prcm)->cm_mpu_m3_clkstctrl,
410 (*prcm)->cm_ivahd_clkstctrl,
411 (*prcm)->cm_dsp_clkstctrl,
412 (*prcm)->cm_dss_clkstctrl,
413 (*prcm)->cm_sgx_clkstctrl,
414 (*prcm)->cm1_abe_clkstctrl,
415 (*prcm)->cm_c2c_clkstctrl,
416 (*prcm)->cm_cam_clkstctrl,
417 (*prcm)->cm_dss_clkstctrl,
418 (*prcm)->cm_sdma_clkstctrl,
422 u32 const clk_modules_hw_auto_non_essential[] = {
423 (*prcm)->cm_l3instr_l3_3_clkctrl,
424 (*prcm)->cm_l3instr_l3_instr_clkctrl,
425 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
426 (*prcm)->cm_l3init_hsi_clkctrl,
430 u32 const clk_modules_explicit_en_non_essential[] = {
431 (*prcm)->cm1_abe_aess_clkctrl,
432 (*prcm)->cm1_abe_pdm_clkctrl,
433 (*prcm)->cm1_abe_dmic_clkctrl,
434 (*prcm)->cm1_abe_mcasp_clkctrl,
435 (*prcm)->cm1_abe_mcbsp1_clkctrl,
436 (*prcm)->cm1_abe_mcbsp2_clkctrl,
437 (*prcm)->cm1_abe_mcbsp3_clkctrl,
438 (*prcm)->cm1_abe_slimbus_clkctrl,
439 (*prcm)->cm1_abe_timer5_clkctrl,
440 (*prcm)->cm1_abe_timer6_clkctrl,
441 (*prcm)->cm1_abe_timer7_clkctrl,
442 (*prcm)->cm1_abe_timer8_clkctrl,
443 (*prcm)->cm1_abe_wdt3_clkctrl,
444 (*prcm)->cm_l4per_gptimer9_clkctrl,
445 (*prcm)->cm_l4per_gptimer10_clkctrl,
446 (*prcm)->cm_l4per_gptimer11_clkctrl,
447 (*prcm)->cm_l4per_gptimer3_clkctrl,
448 (*prcm)->cm_l4per_gptimer4_clkctrl,
449 (*prcm)->cm_l4per_hdq1w_clkctrl,
450 (*prcm)->cm_l4per_mcbsp4_clkctrl,
451 (*prcm)->cm_l4per_mcspi2_clkctrl,
452 (*prcm)->cm_l4per_mcspi3_clkctrl,
453 (*prcm)->cm_l4per_mcspi4_clkctrl,
454 (*prcm)->cm_l4per_mmcsd3_clkctrl,
455 (*prcm)->cm_l4per_mmcsd4_clkctrl,
456 (*prcm)->cm_l4per_mmcsd5_clkctrl,
457 (*prcm)->cm_l4per_uart1_clkctrl,
458 (*prcm)->cm_l4per_uart2_clkctrl,
459 (*prcm)->cm_l4per_uart4_clkctrl,
460 (*prcm)->cm_wkup_keyboard_clkctrl,
461 (*prcm)->cm_wkup_wdtimer2_clkctrl,
462 (*prcm)->cm_cam_iss_clkctrl,
463 (*prcm)->cm_cam_fdif_clkctrl,
464 (*prcm)->cm_dss_dss_clkctrl,
465 (*prcm)->cm_sgx_sgx_clkctrl,
469 /* Enable optional functional clock for ISS */
470 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
472 /* Enable all optional functional clocks of DSS */
473 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
475 do_enable_clocks(clk_domains_non_essential,
476 clk_modules_hw_auto_non_essential,
477 clk_modules_explicit_en_non_essential,
480 /* Put camera module in no sleep mode */
481 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
482 MODULE_CLKCTRL_MODULEMODE_MASK,
483 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
484 MODULE_CLKCTRL_MODULEMODE_SHIFT);
487 void hw_data_init(void)
489 u32 omap_rev = omap_revision();
491 (*prcm) = &omap4_prcm;
496 *dplls_data = &omap4430_dplls_es1;
497 *omap_vcores = &omap4430_volts_es1;
504 *dplls_data = &omap4430_dplls;
505 *omap_vcores = &omap4430_volts;
510 *dplls_data = &omap4460_dplls;
511 *omap_vcores = &omap4460_volts;
515 *dplls_data = &omap4470_dplls;
516 *omap_vcores = &omap4470_volts;
520 printf("\n INVALID OMAP REVISION ");