3 * HW data initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_common.h>
32 #include <asm/arch/clocks.h>
33 #include <asm/omap_gpio.h>
36 struct prcm_regs const **prcm =
37 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
38 struct dplls const **dplls_data =
39 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
40 struct vcores_data const **omap_vcores =
41 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
44 * The M & N values in the following tables are created using the
46 * tools/omap/clocks_get_m_n.c
47 * Please use this tool for creating the table for any new frequency.
50 /* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
51 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
52 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
53 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
54 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
55 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
56 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
57 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
58 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
61 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
62 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
63 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
64 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
65 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
66 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
67 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
68 {800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
69 {125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
72 /* dpll locked at 1200 MHz - MPU clk at 600 MHz */
73 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
74 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
75 {600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
76 {250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
77 {125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
78 {300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
79 {200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
80 {125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
83 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
84 {200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
85 {800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
86 {619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
87 {125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
88 {400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
89 {800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
90 {125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
93 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
94 {127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
95 {762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
96 {635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
97 {635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
98 {381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
99 {254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
100 {496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
103 static const struct dpll_params
104 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
105 {200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */
106 {800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */
107 {619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */
108 {125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */
109 {400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */
110 {800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */
111 {125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */
114 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
115 {64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */
116 {768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */
117 {320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */
118 {40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */
119 {384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */
120 {256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */
121 {20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */
124 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
125 {931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */
126 {931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */
127 {665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */
128 {727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */
129 {931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */
130 {931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */
131 {291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */
134 /* ABE M & N values with sys_clk as source */
135 static const struct dpll_params
136 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
137 {49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
138 {68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
139 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
140 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
141 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
142 {29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
143 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
146 /* ABE M & N values with 32K clock as source */
147 static const struct dpll_params abe_dpll_params_32k_196608khz = {
148 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
151 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
152 {80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
153 {960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
155 {50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
156 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
157 {320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
161 struct dplls omap4430_dplls_es1 = {
162 .mpu = mpu_dpll_params_1200mhz,
163 .core = core_dpll_params_es1_1524mhz,
164 .per = per_dpll_params_1536mhz,
165 .iva = iva_dpll_params_1862mhz,
166 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
167 .abe = abe_dpll_params_sysclk_196608khz,
169 .abe = &abe_dpll_params_32k_196608khz,
171 .usb = usb_dpll_params_1920mhz
174 struct dplls omap4430_dplls = {
175 .mpu = mpu_dpll_params_1600mhz,
176 .core = core_dpll_params_es2_1600mhz_ddr200mhz,
177 .per = per_dpll_params_1536mhz,
178 .iva = iva_dpll_params_1862mhz,
179 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
180 .abe = abe_dpll_params_sysclk_196608khz,
182 .abe = &abe_dpll_params_32k_196608khz,
184 .usb = usb_dpll_params_1920mhz
187 struct dplls omap4460_dplls = {
188 .mpu = mpu_dpll_params_1400mhz,
189 .core = core_dpll_params_1600mhz,
190 .per = per_dpll_params_1536mhz,
191 .iva = iva_dpll_params_1862mhz,
192 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
193 .abe = abe_dpll_params_sysclk_196608khz,
195 .abe = &abe_dpll_params_32k_196608khz,
197 .usb = usb_dpll_params_1920mhz
200 struct pmic_data twl6030_4430es1 = {
201 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
202 .step = 12660, /* 10 mV represented in uV */
203 /* The code starts at 1 not 0 */
207 struct pmic_data twl6030 = {
208 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
209 .step = 12660, /* 10 mV represented in uV */
210 /* The code starts at 1 not 0 */
214 struct pmic_data tps62361 = {
215 .base_offset = TPS62361_BASE_VOLT_MV,
216 .step = 10000, /* 10 mV represented in uV */
218 .gpio = TPS62361_VSEL0_GPIO,
222 struct vcores_data omap4430_volts_es1 = {
224 .mpu.addr = SMPS_REG_ADDR_VCORE1,
225 .mpu.pmic = &twl6030_4430es1,
228 .core.addr = SMPS_REG_ADDR_VCORE3,
229 .core.pmic = &twl6030_4430es1,
232 .mm.addr = SMPS_REG_ADDR_VCORE2,
233 .mm.pmic = &twl6030_4430es1,
236 struct vcores_data omap4430_volts = {
238 .mpu.addr = SMPS_REG_ADDR_VCORE1,
239 .mpu.pmic = &twl6030,
242 .core.addr = SMPS_REG_ADDR_VCORE3,
243 .core.pmic = &twl6030,
246 .mm.addr = SMPS_REG_ADDR_VCORE2,
250 struct vcores_data omap4460_volts = {
252 .mpu.addr = TPS62361_REG_ADDR_SET1,
253 .mpu.pmic = &tps62361,
256 .core.addr = SMPS_REG_ADDR_VCORE1,
257 .core.pmic = &tps62361,
260 .mm.addr = SMPS_REG_ADDR_VCORE2,
261 .mm.pmic = &tps62361,
265 * Enable essential clock domains, modules and
266 * do some additional special settings needed
268 void enable_basic_clocks(void)
270 u32 const clk_domains_essential[] = {
271 (*prcm)->cm_l4per_clkstctrl,
272 (*prcm)->cm_l3init_clkstctrl,
273 (*prcm)->cm_memif_clkstctrl,
274 (*prcm)->cm_l4cfg_clkstctrl,
278 u32 const clk_modules_hw_auto_essential[] = {
279 (*prcm)->cm_l3_2_gpmc_clkctrl,
280 (*prcm)->cm_memif_emif_1_clkctrl,
281 (*prcm)->cm_memif_emif_2_clkctrl,
282 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
283 (*prcm)->cm_wkup_gpio1_clkctrl,
284 (*prcm)->cm_l4per_gpio2_clkctrl,
285 (*prcm)->cm_l4per_gpio3_clkctrl,
286 (*prcm)->cm_l4per_gpio4_clkctrl,
287 (*prcm)->cm_l4per_gpio5_clkctrl,
288 (*prcm)->cm_l4per_gpio6_clkctrl,
292 u32 const clk_modules_explicit_en_essential[] = {
293 (*prcm)->cm_wkup_gptimer1_clkctrl,
294 (*prcm)->cm_l3init_hsmmc1_clkctrl,
295 (*prcm)->cm_l3init_hsmmc2_clkctrl,
296 (*prcm)->cm_l4per_gptimer2_clkctrl,
297 (*prcm)->cm_wkup_wdtimer2_clkctrl,
298 (*prcm)->cm_l4per_uart3_clkctrl,
302 /* Enable optional additional functional clock for GPIO4 */
303 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
304 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
306 /* Enable 96 MHz clock for MMC1 & MMC2 */
307 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
308 HSMMC_CLKCTRL_CLKSEL_MASK);
309 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
310 HSMMC_CLKCTRL_CLKSEL_MASK);
312 /* Select 32KHz clock as the source of GPTIMER1 */
313 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
314 GPTIMER1_CLKCTRL_CLKSEL_MASK);
316 /* Enable optional 48M functional clock for USB PHY */
317 setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
318 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
320 do_enable_clocks(clk_domains_essential,
321 clk_modules_hw_auto_essential,
322 clk_modules_explicit_en_essential,
326 void enable_basic_uboot_clocks(void)
328 u32 const clk_domains_essential[] = {
332 u32 const clk_modules_hw_auto_essential[] = {
333 (*prcm)->cm_l3init_hsusbotg_clkctrl,
334 (*prcm)->cm_l3init_usbphy_clkctrl,
335 (*prcm)->cm_l3init_usbphy_clkctrl,
336 (*prcm)->cm_clksel_usb_60mhz,
337 (*prcm)->cm_l3init_hsusbtll_clkctrl,
341 u32 const clk_modules_explicit_en_essential[] = {
342 (*prcm)->cm_l4per_mcspi1_clkctrl,
343 (*prcm)->cm_l4per_i2c1_clkctrl,
344 (*prcm)->cm_l4per_i2c2_clkctrl,
345 (*prcm)->cm_l4per_i2c3_clkctrl,
346 (*prcm)->cm_l4per_i2c4_clkctrl,
347 (*prcm)->cm_l3init_hsusbhost_clkctrl,
351 do_enable_clocks(clk_domains_essential,
352 clk_modules_hw_auto_essential,
353 clk_modules_explicit_en_essential,
358 * Enable non-essential clock domains, modules and
359 * do some additional special settings needed
361 void enable_non_essential_clocks(void)
363 u32 const clk_domains_non_essential[] = {
364 (*prcm)->cm_mpu_m3_clkstctrl,
365 (*prcm)->cm_ivahd_clkstctrl,
366 (*prcm)->cm_dsp_clkstctrl,
367 (*prcm)->cm_dss_clkstctrl,
368 (*prcm)->cm_sgx_clkstctrl,
369 (*prcm)->cm1_abe_clkstctrl,
370 (*prcm)->cm_c2c_clkstctrl,
371 (*prcm)->cm_cam_clkstctrl,
372 (*prcm)->cm_dss_clkstctrl,
373 (*prcm)->cm_sdma_clkstctrl,
377 u32 const clk_modules_hw_auto_non_essential[] = {
378 (*prcm)->cm_l3instr_l3_3_clkctrl,
379 (*prcm)->cm_l3instr_l3_instr_clkctrl,
380 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
381 (*prcm)->cm_l3init_hsi_clkctrl,
385 u32 const clk_modules_explicit_en_non_essential[] = {
386 (*prcm)->cm1_abe_aess_clkctrl,
387 (*prcm)->cm1_abe_pdm_clkctrl,
388 (*prcm)->cm1_abe_dmic_clkctrl,
389 (*prcm)->cm1_abe_mcasp_clkctrl,
390 (*prcm)->cm1_abe_mcbsp1_clkctrl,
391 (*prcm)->cm1_abe_mcbsp2_clkctrl,
392 (*prcm)->cm1_abe_mcbsp3_clkctrl,
393 (*prcm)->cm1_abe_slimbus_clkctrl,
394 (*prcm)->cm1_abe_timer5_clkctrl,
395 (*prcm)->cm1_abe_timer6_clkctrl,
396 (*prcm)->cm1_abe_timer7_clkctrl,
397 (*prcm)->cm1_abe_timer8_clkctrl,
398 (*prcm)->cm1_abe_wdt3_clkctrl,
399 (*prcm)->cm_l4per_gptimer9_clkctrl,
400 (*prcm)->cm_l4per_gptimer10_clkctrl,
401 (*prcm)->cm_l4per_gptimer11_clkctrl,
402 (*prcm)->cm_l4per_gptimer3_clkctrl,
403 (*prcm)->cm_l4per_gptimer4_clkctrl,
404 (*prcm)->cm_l4per_hdq1w_clkctrl,
405 (*prcm)->cm_l4per_mcbsp4_clkctrl,
406 (*prcm)->cm_l4per_mcspi2_clkctrl,
407 (*prcm)->cm_l4per_mcspi3_clkctrl,
408 (*prcm)->cm_l4per_mcspi4_clkctrl,
409 (*prcm)->cm_l4per_mmcsd3_clkctrl,
410 (*prcm)->cm_l4per_mmcsd4_clkctrl,
411 (*prcm)->cm_l4per_mmcsd5_clkctrl,
412 (*prcm)->cm_l4per_uart1_clkctrl,
413 (*prcm)->cm_l4per_uart2_clkctrl,
414 (*prcm)->cm_l4per_uart4_clkctrl,
415 (*prcm)->cm_wkup_keyboard_clkctrl,
416 (*prcm)->cm_wkup_wdtimer2_clkctrl,
417 (*prcm)->cm_cam_iss_clkctrl,
418 (*prcm)->cm_cam_fdif_clkctrl,
419 (*prcm)->cm_dss_dss_clkctrl,
420 (*prcm)->cm_sgx_sgx_clkctrl,
424 /* Enable optional functional clock for ISS */
425 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
427 /* Enable all optional functional clocks of DSS */
428 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
430 do_enable_clocks(clk_domains_non_essential,
431 clk_modules_hw_auto_non_essential,
432 clk_modules_explicit_en_non_essential,
435 /* Put camera module in no sleep mode */
436 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
437 MODULE_CLKCTRL_MODULEMODE_MASK,
438 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
439 MODULE_CLKCTRL_MODULEMODE_SHIFT);
442 void hw_data_init(void)
444 u32 omap_rev = omap_revision();
446 (*prcm) = &omap4_prcm;
451 *dplls_data = &omap4430_dplls_es1;
452 *omap_vcores = &omap4430_volts_es1;
459 *dplls_data = &omap4430_dplls;
460 *omap_vcores = &omap4430_volts;
465 *dplls_data = &omap4460_dplls;
466 *omap_vcores = &omap4460_volts;
470 printf("\n INVALID OMAP REVISION ");