3 * Common functions for OMAP4 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/armv7.h>
32 #include <asm/arch/cpu.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/sizes.h>
35 #include <asm/arch/emif.h>
36 #include <asm/arch/gpio.h>
37 #include "omap4_mux_data.h"
39 DECLARE_GLOBAL_DATA_PTR;
41 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
43 static const struct gpio_bank gpio_bank_44xx[6] = {
44 { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
45 { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
46 { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
47 { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
48 { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
49 { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
52 const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
54 #ifdef CONFIG_SPL_BUILD
56 * We use static variables because global data is not ready yet.
57 * Initialized data is available in SPL right from the beginning.
58 * We would not typically need to save these parameters in regular
59 * U-Boot. This is needed only in SPL at the moment.
61 u32 omap4_boot_device = BOOT_DEVICE_MMC1;
62 u32 omap4_boot_mode = MMCSD_MODE_FAT;
64 u32 omap_boot_device(void)
66 return omap4_boot_device;
69 u32 omap_boot_mode(void)
71 return omap4_boot_mode;
75 * Some tuning of IOs for optimal power and performance
77 static void do_io_settings(void)
80 struct control_lpddr2io_regs *lpddr2io_regs =
81 (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
82 struct omap4_sys_ctrl_regs *const ctrl =
83 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
85 u32 omap4_rev = omap_revision();
87 if (omap4_rev == OMAP4430_ES1_0)
88 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
89 else if (omap4_rev == OMAP4430_ES2_0)
90 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
92 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
95 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
96 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
97 /* No pull for GR10 as per hw team's recommendation */
98 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
99 &lpddr2io_regs->control_lpddr2io1_2);
100 writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
103 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
104 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
105 /* No pull for GR10 as per hw team's recommendation */
106 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
107 &lpddr2io_regs->control_lpddr2io2_2);
108 writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
111 * Some of these settings (TRIM values) come from eFuse and are
112 * in turn programmed in the eFuse at manufacturing time after
113 * calibration of the device. Do the software over-ride only if
114 * the device is not correctly trimmed
116 if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
118 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
119 &ctrl->control_ldosram_iva_voltage_ctrl);
121 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
122 &ctrl->control_ldosram_mpu_voltage_ctrl);
124 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
125 &ctrl->control_ldosram_core_voltage_ctrl);
128 if (!readl(&ctrl->control_efuse_1))
129 writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
131 if (!readl(&ctrl->control_efuse_2))
132 writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
136 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
139 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
141 for (i = 0; i < size; i++, pad++)
142 writew(pad->val, base + pad->offset);
145 static void set_muxconf_regs_essential(void)
147 do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
148 sizeof(core_padconf_array_essential) /
149 sizeof(struct pad_conf_entry));
151 do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
152 sizeof(wkup_padconf_array_essential) /
153 sizeof(struct pad_conf_entry));
155 /* gpio_wk7 is used for controlling TPS on 4460 */
156 if (omap_revision() >= OMAP4460_ES1_0)
157 writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ);
160 static void set_mux_conf_regs(void)
162 switch (omap4_hw_init_context()) {
163 case OMAP_INIT_CONTEXT_SPL:
164 set_muxconf_regs_essential();
166 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
167 set_muxconf_regs_non_essential();
169 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
170 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
171 set_muxconf_regs_essential();
172 set_muxconf_regs_non_essential();
177 static u32 cortex_a9_rev(void)
182 /* Read Main ID Register (MIDR) */
183 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
188 static void init_omap4_revision(void)
191 * For some of the ES2/ES1 boards ID_CODE is not reliable:
192 * Also, ES1 and ES2 have different ARM revisions
193 * So use ARM revision for identification
195 unsigned int arm_rev = cortex_a9_rev();
198 case MIDR_CORTEX_A9_R0P1:
199 *omap4_revision = OMAP4430_ES1_0;
201 case MIDR_CORTEX_A9_R1P2:
202 switch (readl(CONTROL_ID_CODE)) {
203 case OMAP4_CONTROL_ID_CODE_ES2_0:
204 *omap4_revision = OMAP4430_ES2_0;
206 case OMAP4_CONTROL_ID_CODE_ES2_1:
207 *omap4_revision = OMAP4430_ES2_1;
209 case OMAP4_CONTROL_ID_CODE_ES2_2:
210 *omap4_revision = OMAP4430_ES2_2;
213 *omap4_revision = OMAP4430_ES2_0;
217 case MIDR_CORTEX_A9_R1P3:
218 *omap4_revision = OMAP4430_ES2_3;
220 case MIDR_CORTEX_A9_R2P10:
221 *omap4_revision = OMAP4460_ES1_0;
224 *omap4_revision = OMAP4430_SILICON_ID_INVALID;
229 void omap_rev_string(char *omap4_rev_string)
231 u32 omap4_rev = omap_revision();
232 u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
233 u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
234 u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
236 sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
242 * Description: Does early system init of watchdog, muxing, andclocks
243 * Watchdog disable is done always. For the rest what gets done
244 * depends on the boot mode in which this function is executed
245 * 1. s_init of SPL running from SRAM
246 * 2. s_init of U-Boot running from FLASH
247 * 3. s_init of U-Boot loaded to SDRAM by SPL
248 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
249 * Configuration Header feature
250 * Please have a look at the respective functions to see what gets
251 * done in each of these cases
252 * This function is called with SRAM stack.
256 init_omap4_revision();
259 #ifdef CONFIG_SPL_BUILD
260 setup_clocks_for_console();
261 preloader_console_init();
265 #ifdef CONFIG_SPL_BUILD
266 /* For regular u-boot sdram_init() is called from dram_init() */
272 * Routine: wait_for_command_complete
273 * Description: Wait for posting to finish on watchdog
275 void wait_for_command_complete(struct watchdog *wd_base)
279 pending = readl(&wd_base->wwps);
284 * Routine: watchdog_init
285 * Description: Shut down watch dogs
287 void watchdog_init(void)
289 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
291 writel(WD_UNLOCK1, &wd2_base->wspr);
292 wait_for_command_complete(wd2_base);
293 writel(WD_UNLOCK2, &wd2_base->wspr);
298 * This function finds the SDRAM size available in the system
299 * based on DMM section configurations
300 * This is needed because the size of memory installed may be
301 * different on different versions of the board
303 u32 omap4_sdram_size(void)
305 u32 section, i, total_size = 0, size, addr;
306 for (i = 0; i < 4; i++) {
307 section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
308 addr = section & OMAP44XX_SYS_ADDR_MASK;
309 /* See if the address is valid */
310 if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
311 (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
312 size = ((section & OMAP44XX_SYS_SIZE_MASK) >>
313 OMAP44XX_SYS_SIZE_SHIFT);
325 * Description: sets uboots idea of sdram size
330 gd->ram_size = omap4_sdram_size();
336 * Print board information
340 puts(sysinfo.board_string);
345 * This function is called by start_armboot. You can reliably use static
346 * data. Any boot-time function that require static data should be
349 int arch_cpu_init(void)
354 #ifndef CONFIG_SYS_L2CACHE_OFF
355 void v7_outer_cache_enable(void)
357 set_pl310_ctrl_reg(1);
360 void v7_outer_cache_disable(void)
362 set_pl310_ctrl_reg(0);
366 #ifndef CONFIG_SYS_DCACHE_OFF
367 void enable_caches(void)
369 /* Enable D-cache. I-cache is already enabled in start.S */