arch/arm/cpu/armv7/omap-common/hwinit-common.c

   1 /*
   2  *
   3  * Common functions for OMAP4/5 based boards
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14 #include <common.h>
  15 #include <spl.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <linux/sizes.h>
  18 #include <asm/emif.h>
  19 #include <asm/omap_common.h>
  20 #include <linux/compiler.h>
  21 #include <asm/system.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
  26 {
  27         int i;
  28         struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
  29
  30         for (i = 0; i < size; i++, pad++)
  31                 writew(pad->val, base + pad->offset);
  32 }
  33
  34 static void set_mux_conf_regs(void)
  35 {
  36         switch (omap_hw_init_context()) {
  37         case OMAP_INIT_CONTEXT_SPL:
  38                 set_muxconf_regs_essential();
  39                 break;
  40         case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
  41                 break;
  42         case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  43         case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  44                 set_muxconf_regs_essential();
  45                 break;
  46         }
  47 }
  48
  49 u32 cortex_rev(void)
  50 {
  51
  52         unsigned int rev;
  53
  54         /* Read Main ID Register (MIDR) */
  55         asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
  56
  57         return rev;
  58 }
  59
  60 static void omap_rev_string(void)
  61 {
  62         u32 omap_rev = omap_revision();
  63         u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
  64         u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
  65         u32 major_rev = (omap_rev & 0x00000F00) >> 8;
  66         u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
  67
  68         if (soc_variant)
  69                 printf("OMAP");
  70         else
  71                 printf("DRA");
  72         printf("%x ES%x.%x\n", omap_variant, major_rev,
  73                minor_rev);
  74 }
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 void spl_display_print(void)
  78 {
  79         omap_rev_string();
  80 }
  81 #endif
  82
  83 void __weak srcomp_enable(void)
  84 {
  85 }
  86
  87 #ifdef CONFIG_ARCH_CPU_INIT
  88 /*
  89  * SOC specific cpu init
  90  */
  91 int arch_cpu_init(void)
  92 {
  93         save_omap_boot_params();
  94         return 0;
  95 }
  96 #endif /* CONFIG_ARCH_CPU_INIT */
  97
  98 /*
  99  * Routine: s_init
 100  * Description: Does early system init of watchdog, muxing,  andclocks
 101  * Watchdog disable is done always. For the rest what gets done
 102  * depends on the boot mode in which this function is executed
 103  *   1. s_init of SPL running from SRAM
 104  *   2. s_init of U-Boot running from FLASH
 105  *   3. s_init of U-Boot loaded to SDRAM by SPL
 106  *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
 107  *      Configuration Header feature
 108  * Please have a look at the respective functions to see what gets
 109  * done in each of these cases
 110  * This function is called with SRAM stack.
 111  */
 112 void s_init(void)
 113 {
 114         init_omap_revision();
 115         hw_data_init();
 116
 117 #ifdef CONFIG_SPL_BUILD
 118         if (warm_reset() &&
 119             (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
 120                 force_emif_self_refresh();
 121 #endif
 122         watchdog_init();
 123         set_mux_conf_regs();
 124 #ifdef CONFIG_SPL_BUILD
 125         srcomp_enable();
 126         setup_clocks_for_console();
 127
 128         do_io_settings();
 129 #endif
 130         prcm_init();
 131 }
 132
 133 #ifdef CONFIG_SPL_BUILD
 134 void board_init_f(ulong dummy)
 135 {
 136 #ifdef CONFIG_BOARD_EARLY_INIT_F
 137         board_early_init_f();
 138 #endif
 139         /* For regular u-boot sdram_init() is called from dram_init() */
 140         sdram_init();
 141 }
 142 #endif
 143
 144 /*
 145  * Routine: wait_for_command_complete
 146  * Description: Wait for posting to finish on watchdog
 147  */
 148 void wait_for_command_complete(struct watchdog *wd_base)
 149 {
 150         int pending = 1;
 151         do {
 152                 pending = readl(&wd_base->wwps);
 153         } while (pending);
 154 }
 155
 156 /*
 157  * Routine: watchdog_init
 158  * Description: Shut down watch dogs
 159  */
 160 void watchdog_init(void)
 161 {
 162         struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
 163
 164         writel(WD_UNLOCK1, &wd2_base->wspr);
 165         wait_for_command_complete(wd2_base);
 166         writel(WD_UNLOCK2, &wd2_base->wspr);
 167 }
 168
 169
 170 /*
 171  * This function finds the SDRAM size available in the system
 172  * based on DMM section configurations
 173  * This is needed because the size of memory installed may be
 174  * different on different versions of the board
 175  */
 176 u32 omap_sdram_size(void)
 177 {
 178         u32 section, i, valid;
 179         u64 sdram_start = 0, sdram_end = 0, addr,
 180             size, total_size = 0, trap_size = 0, trap_start = 0;
 181
 182         for (i = 0; i < 4; i++) {
 183                 section = __raw_readl(DMM_BASE + i*4);
 184                 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
 185                         (EMIF_SDRC_ADDRSPC_SHIFT);
 186                 addr = section & EMIF_SYS_ADDR_MASK;
 187
 188                 /* See if the address is valid */
 189                 if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
 190                     (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
 191                         size = ((section & EMIF_SYS_SIZE_MASK) >>
 192                                    EMIF_SYS_SIZE_SHIFT);
 193                         size = 1 << size;
 194                         size *= SZ_16M;
 195
 196                         if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
 197                                 if (!sdram_start || (addr < sdram_start))
 198                                         sdram_start = addr;
 199                                 if (!sdram_end || ((addr + size) > sdram_end))
 200                                         sdram_end = addr + size;
 201                         } else {
 202                                 trap_size = size;
 203                                 trap_start = addr;
 204                         }
 205                 }
 206         }
 207
 208         if ((trap_start >= sdram_start) && (trap_start < sdram_end))
 209                 total_size = (sdram_end - sdram_start) - (trap_size);
 210         else
 211                 total_size = sdram_end - sdram_start;
 212
 213         return total_size;
 214 }
 215
 216
 217 /*
 218  * Routine: dram_init
 219  * Description: sets uboots idea of sdram size
 220  */
 221 int dram_init(void)
 222 {
 223         sdram_init();
 224         gd->ram_size = omap_sdram_size();
 225         return 0;
 226 }
 227
 228 /*
 229  * Print board information
 230  */
 231 int checkboard(void)
 232 {
 233         puts(sysinfo.board_string);
 234         return 0;
 235 }
 236
 237 /*
 238  *  get_device_type(): tell if GP/HS/EMU/TST
 239  */
 240 u32 get_device_type(void)
 241 {
 242         return (readl((*ctrl)->control_status) &
 243                                       (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
 244 }
 245
 246 #if defined(CONFIG_DISPLAY_CPUINFO)
 247 /*
 248  * Print CPU information
 249  */
 250 int print_cpuinfo(void)
 251 {
 252         puts("CPU  : ");
 253         omap_rev_string();
 254
 255         return 0;
 256 }
 257 #endif