5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
34 #include <linux/compiler.h>
36 static int emif1_enabled = -1, emif2_enabled = -1;
38 void set_lpmode_selfrefresh(u32 base)
40 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
43 reg = readl(&emif->emif_pwr_mgmt_ctrl);
44 reg &= ~EMIF_REG_LP_MODE_MASK;
45 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
46 reg &= ~EMIF_REG_SR_TIM_MASK;
47 writel(reg, &emif->emif_pwr_mgmt_ctrl);
49 /* dummy read for the new SR_TIM to be loaded */
50 readl(&emif->emif_pwr_mgmt_ctrl);
53 void force_emif_self_refresh()
55 set_lpmode_selfrefresh(EMIF1_BASE);
56 set_lpmode_selfrefresh(EMIF2_BASE);
59 inline u32 emif_num(u32 base)
61 if (base == EMIF1_BASE)
63 else if (base == EMIF2_BASE)
70 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
73 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
75 mr_addr |= cs << EMIF_REG_CS_SHIFT;
76 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
77 if (omap_revision() == OMAP4430_ES2_0)
78 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
80 mr = readl(&emif->emif_lpddr2_mode_reg_data);
81 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
83 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
84 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
85 ((mr & 0xff000000) >> 24) == (mr & 0xff))
91 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
93 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
95 mr_addr |= cs << EMIF_REG_CS_SHIFT;
96 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
97 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
100 void emif_reset_phy(u32 base)
102 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
105 iodft = readl(&emif->emif_iodft_tlgc);
106 iodft |= EMIF_REG_RESET_PHY_MASK;
107 writel(iodft, &emif->emif_iodft_tlgc);
110 static void do_lpddr2_init(u32 base, u32 cs)
114 /* Wait till device auto initialization is complete */
115 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
117 set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
120 * Enough loops assuming a maximum of 2GHz
125 if (omap_revision() >= OMAP5430_ES1_0)
126 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
128 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
130 set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
133 * Enable refresh along with writing MR2
134 * Encoding of RL in MR2 is (RL - 2)
136 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
137 set_mr(base, cs, mr_addr, RL_FINAL - 2);
139 if (omap_revision() >= OMAP5430_ES1_0)
140 set_mr(base, cs, LPDDR2_MR3, 0x1);
143 static void lpddr2_init(u32 base, const struct emif_regs *regs)
145 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
148 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
151 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
152 * when EMIF_SDRAM_CONFIG register is written
154 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
157 * Set the SDRAM_CONFIG and PHY_CTRL for the
158 * un-locked frequency & default RL
160 writel(regs->sdram_config_init, &emif->emif_sdram_config);
161 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
163 do_ext_phy_settings(base, regs);
165 do_lpddr2_init(base, CS0);
166 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
167 do_lpddr2_init(base, CS1);
169 writel(regs->sdram_config, &emif->emif_sdram_config);
170 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
172 /* Enable refresh now */
173 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
177 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
181 void emif_update_timings(u32 base, const struct emif_regs *regs)
183 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
185 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
186 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
187 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
188 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
189 if (omap_revision() == OMAP4430_ES1_0) {
190 /* ES1 bug EMIF should be in force idle during freq_update */
191 writel(0, &emif->emif_pwr_mgmt_ctrl);
193 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
194 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
196 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
197 writel(regs->zq_config, &emif->emif_zq_config);
198 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
199 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
201 if (omap_revision() >= OMAP5430_ES1_0) {
202 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
203 &emif->emif_l3_config);
204 } else if (omap_revision() >= OMAP4460_ES1_0) {
205 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
206 &emif->emif_l3_config);
208 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
209 &emif->emif_l3_config);
213 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
215 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
217 /* keep sdram in self-refresh */
218 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
219 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
223 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
224 * Invert clock adds an additional half cycle delay on the command
225 * interface. The additional half cycle, is usually meant to enable
226 * leveling in the situation that DQS is later than CK on the board.It
227 * also helps provide some additional margin for leveling.
229 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
230 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
233 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
234 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
236 /* Launch Full leveling */
237 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
239 /* Wait till full leveling is complete */
240 readl(&emif->emif_rd_wr_lvl_ctl);
243 /* Read data eye leveling no of samples */
244 config_data_eye_leveling_samples(base);
246 /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
247 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
250 /* Launch Incremental leveling */
251 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
255 static void ddr3_init(u32 base, const struct emif_regs *regs)
257 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
258 u32 *ext_phy_ctrl_base = 0;
259 u32 *emif_ext_phy_ctrl_base = 0;
263 * Set SDRAM_CONFIG and PHY control registers to locked frequency
264 * and RL =7. As the default values of the Mode Registers are not
265 * defined, contents of mode Registers must be fully initialized.
266 * H/W takes care of this initialization
268 writel(regs->sdram_config_init, &emif->emif_sdram_config);
270 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
272 /* Update timing registers */
273 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
274 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
275 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
277 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
278 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
280 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
281 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
283 /* Configure external phy control timing registers */
284 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
285 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
286 /* Update shadow registers */
287 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
291 * external phy 6-24 registers do not change with
294 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
295 writel(ddr3_ext_phy_ctrl_const_base[i],
296 emif_ext_phy_ctrl_base++);
297 /* Update shadow registers */
298 writel(ddr3_ext_phy_ctrl_const_base[i],
299 emif_ext_phy_ctrl_base++);
302 /* enable leveling */
303 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
305 ddr3_leveling(base, regs);
308 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
309 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
312 * Organization and refresh requirements for LPDDR2 devices of different
313 * types and densities. Derived from JESD209-2 section 2.4
315 const struct lpddr2_addressing addressing_table[] = {
316 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
317 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
318 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
319 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
320 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
321 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
322 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
323 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
324 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
325 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
326 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
329 static const u32 lpddr2_density_2_size_in_mbytes[] = {
343 * Calculate the period of DDR clock from frequency value and set the
344 * denominator and numerator in global variables for easy access later
346 static void set_ddr_clk_period(u32 freq)
350 * period_in_ns = 10^9/freq
354 cancel_out(T_num, T_den, 200);
359 * Convert time in nano seconds to number of cycles of DDR clock
361 static inline u32 ns_2_cycles(u32 ns)
363 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
367 * ns_2_cycles with the difference that the time passed is 2 times the actual
368 * value(to avoid fractions). The cycles returned is for the original value of
369 * the timing parameter
371 static inline u32 ns_x2_2_cycles(u32 ns)
373 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
377 * Find addressing table index based on the device's type(S2 or S4) and
380 s8 addressing_table_index(u8 type, u8 density, u8 width)
383 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
387 * Look at the way ADDR_TABLE_INDEX* values have been defined
388 * in emif.h compared to LPDDR2_DENSITY_* values
389 * The table is layed out in the increasing order of density
390 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
393 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
394 index = ADDR_TABLE_INDEX1GS2;
395 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
396 index = ADDR_TABLE_INDEX2GS2;
400 debug("emif: addressing table index %d\n", index);
406 * Find the the right timing table from the array of timing
407 * tables of the device using DDR clock frequency
409 static const struct lpddr2_ac_timings *get_timings_table(const struct
410 lpddr2_ac_timings const *const *device_timings,
413 u32 i, temp, freq_nearest;
414 const struct lpddr2_ac_timings *timings = 0;
416 emif_assert(freq <= MAX_LPDDR2_FREQ);
417 emif_assert(device_timings);
420 * Start with the maximum allowed frequency - that is always safe
422 freq_nearest = MAX_LPDDR2_FREQ;
424 * Find the timings table that has the max frequency value:
425 * i. Above or equal to the DDR frequency - safe
426 * ii. The lowest that satisfies condition (i) - optimal
428 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
429 temp = device_timings[i]->max_freq;
430 if ((temp >= freq) && (temp <= freq_nearest)) {
432 timings = device_timings[i];
435 debug("emif: timings table: %d\n", freq_nearest);
440 * Finds the value of emif_sdram_config_reg
441 * All parameters are programmed based on the device on CS0.
442 * If there is a device on CS1, it will be same as that on CS0 or
443 * it will be NVM. We don't support NVM yet.
444 * If cs1_device pointer is NULL it is assumed that there is no device
447 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
448 const struct lpddr2_device_details *cs1_device,
449 const struct lpddr2_addressing *addressing,
454 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
455 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
456 EMIF_REG_IBANK_POS_SHIFT;
458 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
460 config_reg |= RL << EMIF_REG_CL_SHIFT;
462 config_reg |= addressing->row_sz[cs0_device->io_width] <<
463 EMIF_REG_ROWSIZE_SHIFT;
465 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
467 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
468 EMIF_REG_EBANK_SHIFT;
470 config_reg |= addressing->col_sz[cs0_device->io_width] <<
471 EMIF_REG_PAGESIZE_SHIFT;
476 static u32 get_sdram_ref_ctrl(u32 freq,
477 const struct lpddr2_addressing *addressing)
479 u32 ref_ctrl = 0, val = 0, freq_khz;
480 freq_khz = freq / 1000;
482 * refresh rate to be set is 'tREFI * freq in MHz
483 * division by 10000 to account for khz and x10 in t_REFI_us_x10
485 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
486 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
491 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
492 const struct lpddr2_min_tck *min_tck,
493 const struct lpddr2_addressing *addressing)
495 u32 tim1 = 0, val = 0;
496 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
497 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
499 if (addressing->num_banks == BANKS8)
500 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
503 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
505 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
507 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
508 tim1 |= val << EMIF_REG_T_RC_SHIFT;
510 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
511 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
513 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
514 tim1 |= val << EMIF_REG_T_WR_SHIFT;
516 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
517 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
519 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
520 tim1 |= val << EMIF_REG_T_RP_SHIFT;
525 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
526 const struct lpddr2_min_tck *min_tck)
528 u32 tim2 = 0, val = 0;
529 val = max(min_tck->tCKE, timings->tCKE) - 1;
530 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
532 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
533 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
536 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
539 val = ns_2_cycles(timings->tXSR) - 1;
540 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
541 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
543 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
544 tim2 |= val << EMIF_REG_T_XP_SHIFT;
549 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
550 const struct lpddr2_min_tck *min_tck,
551 const struct lpddr2_addressing *addressing)
553 u32 tim3 = 0, val = 0;
554 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
555 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
557 val = ns_2_cycles(timings->tRFCab) - 1;
558 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
560 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
561 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
563 val = ns_2_cycles(timings->tZQCS) - 1;
564 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
566 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
567 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
572 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
573 const struct lpddr2_addressing *addressing,
579 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
580 addressing->t_REFI_us_x10;
583 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
584 addressing->t_REFI_us_x10;
585 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
587 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
589 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
591 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
594 * Assuming that two chipselects have a single calibration resistor
595 * If there are indeed two calibration resistors, then this flag should
596 * be enabled to take advantage of dual calibration feature.
597 * This data should ideally come from board files. But considering
598 * that none of the boards today have calibration resistors per CS,
599 * it would be an unnecessary overhead.
601 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
603 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
605 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
610 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
611 const struct lpddr2_addressing *addressing,
614 u32 alert = 0, interval;
616 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
619 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
621 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
623 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
625 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
627 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
629 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
634 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
636 u32 idle = 0, val = 0;
638 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
640 /*Maximum value in normal conditions - suggested by hw team */
642 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
644 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
649 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
651 u32 phy = 0, val = 0;
653 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
655 if (freq <= 100000000)
656 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
657 else if (freq <= 200000000)
658 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
660 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
661 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
663 /* Other fields are constant magic values. Hardcode them together */
664 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
665 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
670 static u32 get_emif_mem_size(struct emif_device_details *devices)
672 u32 size_mbytes = 0, temp;
677 if (devices->cs0_device_details) {
678 temp = devices->cs0_device_details->density;
679 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
682 if (devices->cs1_device_details) {
683 temp = devices->cs1_device_details->density;
684 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
686 /* convert to bytes */
687 return size_mbytes << 20;
690 /* Gets the encoding corresponding to a given DMM section size */
691 u32 get_dmm_section_size_map(u32 section_size)
694 * Section size mapping:
695 * 0x0: 16-MiB section
696 * 0x1: 32-MiB section
697 * 0x2: 64-MiB section
698 * 0x3: 128-MiB section
699 * 0x4: 256-MiB section
700 * 0x5: 512-MiB section
704 section_size >>= 24; /* divide by 16 MB */
705 return log_2_n_round_down(section_size);
708 static void emif_calculate_regs(
709 const struct emif_device_details *emif_dev_details,
710 u32 freq, struct emif_regs *regs)
713 const struct lpddr2_addressing *addressing;
714 const struct lpddr2_ac_timings *timings;
715 const struct lpddr2_min_tck *min_tck;
716 const struct lpddr2_device_details *cs0_dev_details =
717 emif_dev_details->cs0_device_details;
718 const struct lpddr2_device_details *cs1_dev_details =
719 emif_dev_details->cs1_device_details;
720 const struct lpddr2_device_timings *cs0_dev_timings =
721 emif_dev_details->cs0_device_timings;
723 emif_assert(emif_dev_details);
726 * You can not have a device on CS1 without one on CS0
727 * So configuring EMIF without a device on CS0 doesn't
730 emif_assert(cs0_dev_details);
731 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
733 * If there is a device on CS1 it should be same type as CS0
734 * (or NVM. But NVM is not supported in this driver yet)
736 emif_assert((cs1_dev_details == NULL) ||
737 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
738 (cs0_dev_details->type == cs1_dev_details->type));
739 emif_assert(freq <= MAX_LPDDR2_FREQ);
741 set_ddr_clk_period(freq);
744 * The device on CS0 is used for all timing calculations
745 * There is only one set of registers for timings per EMIF. So, if the
746 * second CS(CS1) has a device, it should have the same timings as the
749 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
750 emif_assert(timings);
751 min_tck = cs0_dev_timings->min_tck;
753 temp = addressing_table_index(cs0_dev_details->type,
754 cs0_dev_details->density,
755 cs0_dev_details->io_width);
757 emif_assert((temp >= 0));
758 addressing = &(addressing_table[temp]);
759 emif_assert(addressing);
761 sys_freq = get_sys_clk_freq();
763 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
765 addressing, RL_BOOT);
767 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
769 addressing, RL_FINAL);
771 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
773 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
775 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
777 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
779 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
781 regs->temp_alert_config =
782 get_temp_alert_config(cs1_dev_details, addressing, 0);
784 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
785 LPDDR2_VOLTAGE_STABLE);
787 regs->emif_ddr_phy_ctlr_1_init =
788 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
790 regs->emif_ddr_phy_ctlr_1 =
791 get_ddr_phy_ctrl_1(freq, RL_FINAL);
795 print_timing_reg(regs->sdram_config_init);
796 print_timing_reg(regs->sdram_config);
797 print_timing_reg(regs->ref_ctrl);
798 print_timing_reg(regs->sdram_tim1);
799 print_timing_reg(regs->sdram_tim2);
800 print_timing_reg(regs->sdram_tim3);
801 print_timing_reg(regs->read_idle_ctrl);
802 print_timing_reg(regs->temp_alert_config);
803 print_timing_reg(regs->zq_config);
804 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
805 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
807 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
809 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
810 const char *get_lpddr2_type(u8 type_id)
822 const char *get_lpddr2_io_width(u8 width_id)
825 case LPDDR2_IO_WIDTH_8:
827 case LPDDR2_IO_WIDTH_16:
829 case LPDDR2_IO_WIDTH_32:
836 const char *get_lpddr2_manufacturer(u32 manufacturer)
838 switch (manufacturer) {
839 case LPDDR2_MANUFACTURER_SAMSUNG:
841 case LPDDR2_MANUFACTURER_QIMONDA:
843 case LPDDR2_MANUFACTURER_ELPIDA:
845 case LPDDR2_MANUFACTURER_ETRON:
847 case LPDDR2_MANUFACTURER_NANYA:
849 case LPDDR2_MANUFACTURER_HYNIX:
851 case LPDDR2_MANUFACTURER_MOSEL:
853 case LPDDR2_MANUFACTURER_WINBOND:
855 case LPDDR2_MANUFACTURER_ESMT:
857 case LPDDR2_MANUFACTURER_SPANSION:
859 case LPDDR2_MANUFACTURER_SST:
861 case LPDDR2_MANUFACTURER_ZMOS:
863 case LPDDR2_MANUFACTURER_INTEL:
865 case LPDDR2_MANUFACTURER_NUMONYX:
867 case LPDDR2_MANUFACTURER_MICRON:
874 static void display_sdram_details(u32 emif_nr, u32 cs,
875 struct lpddr2_device_details *device)
878 const char *type_str;
879 char density_str[10];
882 debug("EMIF%d CS%d\t", emif_nr, cs);
889 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
890 type_str = get_lpddr2_type(device->type);
892 density = lpddr2_density_2_size_in_mbytes[device->density];
893 if ((density / 1024 * 1024) == density) {
895 sprintf(density_str, "%d GB", density);
897 sprintf(density_str, "%d MB", density);
898 if (mfg_str && type_str)
899 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
902 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
903 struct lpddr2_device_details *lpddr2_device)
907 mr = get_mr(base, cs, LPDDR2_MR0);
909 /* Mode register value bigger than 8 bit */
913 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
918 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
921 /* DNV supported - But DNV is only supported for NVM */
925 mr = get_mr(base, cs, LPDDR2_MR4);
927 /* Mode register value bigger than 8 bit */
931 mr = get_mr(base, cs, LPDDR2_MR5);
933 /* Mode register value bigger than 8 bit */
937 if (!get_lpddr2_manufacturer(mr)) {
938 /* Manufacturer not identified */
941 lpddr2_device->manufacturer = mr;
943 mr = get_mr(base, cs, LPDDR2_MR6);
945 /* Mode register value bigger than 8 bit */
949 mr = get_mr(base, cs, LPDDR2_MR7);
951 /* Mode register value bigger than 8 bit */
955 mr = get_mr(base, cs, LPDDR2_MR8);
957 /* Mode register value bigger than 8 bit */
961 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
962 if (!get_lpddr2_type(temp)) {
966 lpddr2_device->type = temp;
968 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
969 if (temp > LPDDR2_DENSITY_32Gb) {
970 /* Density not supported */
973 lpddr2_device->density = temp;
975 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
976 if (!get_lpddr2_io_width(temp)) {
977 /* IO width unsupported value */
980 lpddr2_device->io_width = temp;
983 * If all the above tests pass we should
984 * have a device on this chip-select
989 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
990 struct lpddr2_device_details *lpddr2_dev_details)
993 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
995 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
997 if (!lpddr2_dev_details)
1000 /* Do the minimum init for mode register accesses */
1001 if (!(running_from_sdram() || warm_reset())) {
1002 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1003 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1006 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1009 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1011 return lpddr2_dev_details;
1013 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1015 static void do_sdram_init(u32 base)
1017 const struct emif_regs *regs;
1018 u32 in_sdram, emif_nr;
1020 debug(">>do_sdram_init() %x\n", base);
1022 in_sdram = running_from_sdram();
1023 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1025 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1026 emif_get_reg_dump(emif_nr, ®s);
1028 debug("EMIF: reg dump not provided\n");
1033 * The user has not provided the register values. We need to
1034 * calculate it based on the timings and the DDR frequency
1036 struct emif_device_details dev_details;
1037 struct emif_regs calculated_regs;
1040 * Get device details:
1041 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1042 * - Obtained from user otherwise
1044 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1045 emif_reset_phy(base);
1046 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1048 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1050 emif_reset_phy(base);
1052 /* Return if no devices on this EMIF */
1053 if (!dev_details.cs0_device_details &&
1054 !dev_details.cs1_device_details) {
1055 emif_sizes[emif_nr - 1] = 0;
1060 emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
1063 * Get device timings:
1064 * - Default timings specified by JESD209-2 if
1065 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1066 * - Obtained from user otherwise
1068 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1069 &dev_details.cs1_device_timings);
1071 /* Calculate the register values */
1072 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1073 regs = &calculated_regs;
1074 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1077 * Initializing the LPDDR2 device can not happen from SDRAM.
1078 * Changing the timing registers in EMIF can happen(going from one
1081 if (!(in_sdram || warm_reset())) {
1082 if (omap_revision() != OMAP5432_ES1_0)
1083 lpddr2_init(base, regs);
1085 ddr3_init(base, regs);
1088 /* Write to the shadow registers */
1089 emif_update_timings(base, regs);
1091 debug("<<do_sdram_init() %x\n", base);
1094 void emif_post_init_config(u32 base)
1096 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1097 u32 omap_rev = omap_revision();
1099 if (omap_rev == OMAP5430_ES1_0)
1102 /* reset phy on ES2.0 */
1103 if (omap_rev == OMAP4430_ES2_0)
1104 emif_reset_phy(base);
1106 /* Put EMIF back in smart idle on ES1.0 */
1107 if (omap_rev == OMAP4430_ES1_0)
1108 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1111 void dmm_init(u32 base)
1113 const struct dmm_lisa_map_regs *lisa_map_regs;
1114 u32 i, section, valid;
1116 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1117 emif_get_dmm_regs(&lisa_map_regs);
1119 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1120 u32 section_cnt, sys_addr;
1121 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1125 sys_addr = CONFIG_SYS_SDRAM_BASE;
1126 emif1_size = emif_sizes[0];
1127 emif2_size = emif_sizes[1];
1128 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1130 if (!emif1_size && !emif2_size)
1133 /* symmetric interleaved section */
1134 if (emif1_size && emif2_size) {
1135 mapped_size = min(emif1_size, emif2_size);
1136 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1137 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1139 section_map |= (sys_addr >> 24) <<
1140 EMIF_SYS_ADDR_SHIFT;
1141 section_map |= get_dmm_section_size_map(mapped_size * 2)
1142 << EMIF_SYS_SIZE_SHIFT;
1143 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1144 emif1_size -= mapped_size;
1145 emif2_size -= mapped_size;
1146 sys_addr += (mapped_size * 2);
1151 * Single EMIF section(we can have a maximum of 1 single EMIF
1152 * section- either EMIF1 or EMIF2 or none, but not both)
1155 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1156 section_map |= get_dmm_section_size_map(emif1_size)
1157 << EMIF_SYS_SIZE_SHIFT;
1159 section_map |= (mapped_size >> 24) <<
1160 EMIF_SDRC_ADDR_SHIFT;
1162 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1166 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1167 section_map |= get_dmm_section_size_map(emif2_size) <<
1168 EMIF_SYS_SIZE_SHIFT;
1170 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1172 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1176 if (section_cnt == 2) {
1177 /* Only 1 section - either symmetric or single EMIF */
1178 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1179 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1180 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1182 /* 2 sections - 1 symmetric, 1 single EMIF */
1183 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1184 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1187 /* TRAP for invalid TILER mappings in section 0 */
1188 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1190 lisa_map_regs = &lis_map_regs_calculated;
1192 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1193 (struct dmm_lisa_map_regs *)base;
1195 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1196 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1197 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1198 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1200 writel(lisa_map_regs->dmm_lisa_map_3,
1201 &hw_lisa_map_regs->dmm_lisa_map_3);
1202 writel(lisa_map_regs->dmm_lisa_map_2,
1203 &hw_lisa_map_regs->dmm_lisa_map_2);
1204 writel(lisa_map_regs->dmm_lisa_map_1,
1205 &hw_lisa_map_regs->dmm_lisa_map_1);
1206 writel(lisa_map_regs->dmm_lisa_map_0,
1207 &hw_lisa_map_regs->dmm_lisa_map_0);
1209 if (omap_revision() >= OMAP4460_ES1_0) {
1211 (struct dmm_lisa_map_regs *)MA_BASE;
1213 writel(lisa_map_regs->dmm_lisa_map_3,
1214 &hw_lisa_map_regs->dmm_lisa_map_3);
1215 writel(lisa_map_regs->dmm_lisa_map_2,
1216 &hw_lisa_map_regs->dmm_lisa_map_2);
1217 writel(lisa_map_regs->dmm_lisa_map_1,
1218 &hw_lisa_map_regs->dmm_lisa_map_1);
1219 writel(lisa_map_regs->dmm_lisa_map_0,
1220 &hw_lisa_map_regs->dmm_lisa_map_0);
1224 * EMIF should be configured only when
1225 * memory is mapped on it. Using emif1_enabled
1226 * and emif2_enabled variables for this.
1230 for (i = 0; i < 4; i++) {
1231 section = __raw_readl(DMM_BASE + i*4);
1232 valid = (section & EMIF_SDRC_MAP_MASK) >>
1233 (EMIF_SDRC_MAP_SHIFT);
1238 } else if (valid == 1) {
1240 } else if (valid == 2) {
1248 * SDRAM initialization:
1249 * SDRAM initialization has two parts:
1250 * 1. Configuring the SDRAM device
1251 * 2. Update the AC timings related parameters in the EMIF module
1252 * (1) should be done only once and should not be done while we are
1253 * running from SDRAM.
1254 * (2) can and should be done more than once if OPP changes.
1255 * Particularly, this may be needed when we boot without SPL and
1256 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1257 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1258 * the frequency. So,
1259 * Doing (1) and (2) makes sense - first time initialization
1260 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1261 * Doing (1) and not (2) doen't make sense
1262 * See do_sdram_init() for the details
1264 void sdram_init(void)
1266 u32 in_sdram, size_prog, size_detect;
1267 u32 omap_rev = omap_revision();
1269 debug(">>sdram_init()\n");
1271 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1274 in_sdram = running_from_sdram();
1275 debug("in_sdram = %d\n", in_sdram);
1277 if (!(in_sdram || warm_reset())) {
1278 if (omap_rev != OMAP5432_ES1_0)
1279 bypass_dpll(&prcm->cm_clkmode_dpll_core);
1281 writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
1288 do_sdram_init(EMIF1_BASE);
1291 do_sdram_init(EMIF2_BASE);
1293 if (!(in_sdram || warm_reset())) {
1295 emif_post_init_config(EMIF1_BASE);
1297 emif_post_init_config(EMIF2_BASE);
1300 /* for the shadow registers to take effect */
1301 if (omap_rev != OMAP5432_ES1_0)
1304 /* Do some testing after the init */
1306 size_prog = omap_sdram_size();
1307 size_prog = log_2_n_round_down(size_prog);
1308 size_prog = (1 << size_prog);
1310 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1312 /* Compare with the size programmed */
1313 if (size_detect != size_prog) {
1314 printf("SDRAM: identified size not same as expected"
1315 " size identified: %x expected: %x\n",
1319 debug("get_ram_size() successful");
1322 debug("<<sdram_init()\n");