5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
35 inline u32 emif_num(u32 base)
37 if (base == EMIF1_BASE)
39 else if (base == EMIF2_BASE)
46 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
49 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
51 mr_addr |= cs << EMIF_REG_CS_SHIFT;
52 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
53 if (omap_revision() == OMAP4430_ES2_0)
54 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
56 mr = readl(&emif->emif_lpddr2_mode_reg_data);
57 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
62 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
64 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
66 mr_addr |= cs << EMIF_REG_CS_SHIFT;
67 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
68 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
71 void emif_reset_phy(u32 base)
73 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
76 iodft = readl(&emif->emif_iodft_tlgc);
77 iodft |= EMIF_REG_RESET_PHY_MASK;
78 writel(iodft, &emif->emif_iodft_tlgc);
81 static void do_lpddr2_init(u32 base, u32 cs)
85 /* Wait till device auto initialization is complete */
86 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
88 set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
91 * Enough loops assuming a maximum of 2GHz
96 if (omap_revision() >= OMAP5430_ES1_0)
97 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
99 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
101 set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
104 * Enable refresh along with writing MR2
105 * Encoding of RL in MR2 is (RL - 2)
107 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
108 set_mr(base, cs, mr_addr, RL_FINAL - 2);
110 if (omap_revision() >= OMAP5430_ES1_0)
111 set_mr(base, cs, LPDDR2_MR3, 0x1);
114 static void lpddr2_init(u32 base, const struct emif_regs *regs)
116 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
117 u32 *ext_phy_ctrl_base = 0;
118 u32 *emif_ext_phy_ctrl_base = 0;
122 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
125 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
126 * when EMIF_SDRAM_CONFIG register is written
128 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
131 * Set the SDRAM_CONFIG and PHY_CTRL for the
132 * un-locked frequency & default RL
134 writel(regs->sdram_config_init, &emif->emif_sdram_config);
135 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
137 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
138 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
140 if (omap_revision() >= OMAP5430_ES1_0) {
141 /* Configure external phy control timing registers */
142 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
143 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
144 /* Update shadow registers */
145 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
149 * external phy 6-24 registers do not change with
152 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
153 writel(ext_phy_ctrl_const_base[i],
154 emif_ext_phy_ctrl_base++);
155 /* Update shadow registers */
156 writel(ext_phy_ctrl_const_base[i],
157 emif_ext_phy_ctrl_base++);
161 do_lpddr2_init(base, CS0);
162 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
163 do_lpddr2_init(base, CS1);
165 writel(regs->sdram_config, &emif->emif_sdram_config);
166 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
168 /* Enable refresh now */
169 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
173 void emif_update_timings(u32 base, const struct emif_regs *regs)
175 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
177 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
178 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
179 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
180 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
181 if (omap_revision() == OMAP4430_ES1_0) {
182 /* ES1 bug EMIF should be in force idle during freq_update */
183 writel(0, &emif->emif_pwr_mgmt_ctrl);
185 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
186 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
188 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
189 writel(regs->zq_config, &emif->emif_zq_config);
190 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
191 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
193 if (omap_revision() >= OMAP5430_ES1_0) {
194 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
195 &emif->emif_l3_config);
196 } else if (omap_revision() >= OMAP4460_ES1_0) {
197 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
198 &emif->emif_l3_config);
200 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
201 &emif->emif_l3_config);
205 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
207 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
209 /* keep sdram in self-refresh */
210 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
211 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
215 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
216 * Invert clock adds an additional half cycle delay on the command
217 * interface. The additional half cycle, is usually meant to enable
218 * leveling in the situation that DQS is later than CK on the board.It
219 * also helps provide some additional margin for leveling.
221 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
222 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
225 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
226 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
228 /* Launch Full leveling */
229 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
231 /* Wait till full leveling is complete */
232 readl(&emif->emif_rd_wr_lvl_ctl);
235 /* Read data eye leveling no of samples */
236 config_data_eye_leveling_samples(base);
238 /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
239 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
242 /* Launch Incremental leveling */
243 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
247 static void ddr3_init(u32 base, const struct emif_regs *regs)
249 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
250 u32 *ext_phy_ctrl_base = 0;
251 u32 *emif_ext_phy_ctrl_base = 0;
255 * Set SDRAM_CONFIG and PHY control registers to locked frequency
256 * and RL =7. As the default values of the Mode Registers are not
257 * defined, contents of mode Registers must be fully initialized.
258 * H/W takes care of this initialization
260 writel(regs->sdram_config_init, &emif->emif_sdram_config);
262 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
264 /* Update timing registers */
265 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
266 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
267 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
269 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
270 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
272 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
273 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
275 /* Configure external phy control timing registers */
276 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
277 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
278 /* Update shadow registers */
279 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
283 * external phy 6-24 registers do not change with
286 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
287 writel(ddr3_ext_phy_ctrl_const_base[i],
288 emif_ext_phy_ctrl_base++);
289 /* Update shadow registers */
290 writel(ddr3_ext_phy_ctrl_const_base[i],
291 emif_ext_phy_ctrl_base++);
294 /* enable leveling */
295 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
297 ddr3_leveling(base, regs);
300 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
301 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
304 * Organization and refresh requirements for LPDDR2 devices of different
305 * types and densities. Derived from JESD209-2 section 2.4
307 const struct lpddr2_addressing addressing_table[] = {
308 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
309 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
310 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
311 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
312 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
313 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
314 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
315 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
316 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
317 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
318 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
321 static const u32 lpddr2_density_2_size_in_mbytes[] = {
335 * Calculate the period of DDR clock from frequency value and set the
336 * denominator and numerator in global variables for easy access later
338 static void set_ddr_clk_period(u32 freq)
342 * period_in_ns = 10^9/freq
346 cancel_out(T_num, T_den, 200);
351 * Convert time in nano seconds to number of cycles of DDR clock
353 static inline u32 ns_2_cycles(u32 ns)
355 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
359 * ns_2_cycles with the difference that the time passed is 2 times the actual
360 * value(to avoid fractions). The cycles returned is for the original value of
361 * the timing parameter
363 static inline u32 ns_x2_2_cycles(u32 ns)
365 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
369 * Find addressing table index based on the device's type(S2 or S4) and
372 s8 addressing_table_index(u8 type, u8 density, u8 width)
375 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
379 * Look at the way ADDR_TABLE_INDEX* values have been defined
380 * in emif.h compared to LPDDR2_DENSITY_* values
381 * The table is layed out in the increasing order of density
382 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
385 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
386 index = ADDR_TABLE_INDEX1GS2;
387 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
388 index = ADDR_TABLE_INDEX2GS2;
392 debug("emif: addressing table index %d\n", index);
398 * Find the the right timing table from the array of timing
399 * tables of the device using DDR clock frequency
401 static const struct lpddr2_ac_timings *get_timings_table(const struct
402 lpddr2_ac_timings const *const *device_timings,
405 u32 i, temp, freq_nearest;
406 const struct lpddr2_ac_timings *timings = 0;
408 emif_assert(freq <= MAX_LPDDR2_FREQ);
409 emif_assert(device_timings);
412 * Start with the maximum allowed frequency - that is always safe
414 freq_nearest = MAX_LPDDR2_FREQ;
416 * Find the timings table that has the max frequency value:
417 * i. Above or equal to the DDR frequency - safe
418 * ii. The lowest that satisfies condition (i) - optimal
420 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
421 temp = device_timings[i]->max_freq;
422 if ((temp >= freq) && (temp <= freq_nearest)) {
424 timings = device_timings[i];
427 debug("emif: timings table: %d\n", freq_nearest);
432 * Finds the value of emif_sdram_config_reg
433 * All parameters are programmed based on the device on CS0.
434 * If there is a device on CS1, it will be same as that on CS0 or
435 * it will be NVM. We don't support NVM yet.
436 * If cs1_device pointer is NULL it is assumed that there is no device
439 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
440 const struct lpddr2_device_details *cs1_device,
441 const struct lpddr2_addressing *addressing,
446 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
447 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
448 EMIF_REG_IBANK_POS_SHIFT;
450 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
452 config_reg |= RL << EMIF_REG_CL_SHIFT;
454 config_reg |= addressing->row_sz[cs0_device->io_width] <<
455 EMIF_REG_ROWSIZE_SHIFT;
457 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
459 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
460 EMIF_REG_EBANK_SHIFT;
462 config_reg |= addressing->col_sz[cs0_device->io_width] <<
463 EMIF_REG_PAGESIZE_SHIFT;
468 static u32 get_sdram_ref_ctrl(u32 freq,
469 const struct lpddr2_addressing *addressing)
471 u32 ref_ctrl = 0, val = 0, freq_khz;
472 freq_khz = freq / 1000;
474 * refresh rate to be set is 'tREFI * freq in MHz
475 * division by 10000 to account for khz and x10 in t_REFI_us_x10
477 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
478 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
483 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
484 const struct lpddr2_min_tck *min_tck,
485 const struct lpddr2_addressing *addressing)
487 u32 tim1 = 0, val = 0;
488 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
489 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
491 if (addressing->num_banks == BANKS8)
492 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
495 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
497 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
499 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
500 tim1 |= val << EMIF_REG_T_RC_SHIFT;
502 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
503 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
505 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
506 tim1 |= val << EMIF_REG_T_WR_SHIFT;
508 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
509 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
511 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
512 tim1 |= val << EMIF_REG_T_RP_SHIFT;
517 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
518 const struct lpddr2_min_tck *min_tck)
520 u32 tim2 = 0, val = 0;
521 val = max(min_tck->tCKE, timings->tCKE) - 1;
522 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
524 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
525 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
528 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
531 val = ns_2_cycles(timings->tXSR) - 1;
532 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
533 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
535 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
536 tim2 |= val << EMIF_REG_T_XP_SHIFT;
541 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
542 const struct lpddr2_min_tck *min_tck,
543 const struct lpddr2_addressing *addressing)
545 u32 tim3 = 0, val = 0;
546 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
547 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
549 val = ns_2_cycles(timings->tRFCab) - 1;
550 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
552 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
553 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
555 val = ns_2_cycles(timings->tZQCS) - 1;
556 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
558 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
559 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
564 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
565 const struct lpddr2_addressing *addressing,
571 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
572 addressing->t_REFI_us_x10;
575 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
576 addressing->t_REFI_us_x10;
577 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
579 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
581 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
583 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
586 * Assuming that two chipselects have a single calibration resistor
587 * If there are indeed two calibration resistors, then this flag should
588 * be enabled to take advantage of dual calibration feature.
589 * This data should ideally come from board files. But considering
590 * that none of the boards today have calibration resistors per CS,
591 * it would be an unnecessary overhead.
593 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
595 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
597 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
602 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
603 const struct lpddr2_addressing *addressing,
606 u32 alert = 0, interval;
608 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
611 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
613 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
615 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
617 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
619 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
621 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
626 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
628 u32 idle = 0, val = 0;
630 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
632 /*Maximum value in normal conditions - suggested by hw team */
634 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
636 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
641 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
643 u32 phy = 0, val = 0;
645 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
647 if (freq <= 100000000)
648 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
649 else if (freq <= 200000000)
650 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
652 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
653 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
655 /* Other fields are constant magic values. Hardcode them together */
656 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
657 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
662 static u32 get_emif_mem_size(struct emif_device_details *devices)
664 u32 size_mbytes = 0, temp;
669 if (devices->cs0_device_details) {
670 temp = devices->cs0_device_details->density;
671 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
674 if (devices->cs1_device_details) {
675 temp = devices->cs1_device_details->density;
676 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
678 /* convert to bytes */
679 return size_mbytes << 20;
682 /* Gets the encoding corresponding to a given DMM section size */
683 u32 get_dmm_section_size_map(u32 section_size)
686 * Section size mapping:
687 * 0x0: 16-MiB section
688 * 0x1: 32-MiB section
689 * 0x2: 64-MiB section
690 * 0x3: 128-MiB section
691 * 0x4: 256-MiB section
692 * 0x5: 512-MiB section
696 section_size >>= 24; /* divide by 16 MB */
697 return log_2_n_round_down(section_size);
700 static void emif_calculate_regs(
701 const struct emif_device_details *emif_dev_details,
702 u32 freq, struct emif_regs *regs)
705 const struct lpddr2_addressing *addressing;
706 const struct lpddr2_ac_timings *timings;
707 const struct lpddr2_min_tck *min_tck;
708 const struct lpddr2_device_details *cs0_dev_details =
709 emif_dev_details->cs0_device_details;
710 const struct lpddr2_device_details *cs1_dev_details =
711 emif_dev_details->cs1_device_details;
712 const struct lpddr2_device_timings *cs0_dev_timings =
713 emif_dev_details->cs0_device_timings;
715 emif_assert(emif_dev_details);
718 * You can not have a device on CS1 without one on CS0
719 * So configuring EMIF without a device on CS0 doesn't
722 emif_assert(cs0_dev_details);
723 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
725 * If there is a device on CS1 it should be same type as CS0
726 * (or NVM. But NVM is not supported in this driver yet)
728 emif_assert((cs1_dev_details == NULL) ||
729 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
730 (cs0_dev_details->type == cs1_dev_details->type));
731 emif_assert(freq <= MAX_LPDDR2_FREQ);
733 set_ddr_clk_period(freq);
736 * The device on CS0 is used for all timing calculations
737 * There is only one set of registers for timings per EMIF. So, if the
738 * second CS(CS1) has a device, it should have the same timings as the
741 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
742 emif_assert(timings);
743 min_tck = cs0_dev_timings->min_tck;
745 temp = addressing_table_index(cs0_dev_details->type,
746 cs0_dev_details->density,
747 cs0_dev_details->io_width);
749 emif_assert((temp >= 0));
750 addressing = &(addressing_table[temp]);
751 emif_assert(addressing);
753 sys_freq = get_sys_clk_freq();
755 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
757 addressing, RL_BOOT);
759 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
761 addressing, RL_FINAL);
763 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
765 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
767 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
769 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
771 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
773 regs->temp_alert_config =
774 get_temp_alert_config(cs1_dev_details, addressing, 0);
776 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
777 LPDDR2_VOLTAGE_STABLE);
779 regs->emif_ddr_phy_ctlr_1_init =
780 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
782 regs->emif_ddr_phy_ctlr_1 =
783 get_ddr_phy_ctrl_1(freq, RL_FINAL);
787 print_timing_reg(regs->sdram_config_init);
788 print_timing_reg(regs->sdram_config);
789 print_timing_reg(regs->ref_ctrl);
790 print_timing_reg(regs->sdram_tim1);
791 print_timing_reg(regs->sdram_tim2);
792 print_timing_reg(regs->sdram_tim3);
793 print_timing_reg(regs->read_idle_ctrl);
794 print_timing_reg(regs->temp_alert_config);
795 print_timing_reg(regs->zq_config);
796 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
797 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
799 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
801 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
802 const char *get_lpddr2_type(u8 type_id)
814 const char *get_lpddr2_io_width(u8 width_id)
817 case LPDDR2_IO_WIDTH_8:
819 case LPDDR2_IO_WIDTH_16:
821 case LPDDR2_IO_WIDTH_32:
828 const char *get_lpddr2_manufacturer(u32 manufacturer)
830 switch (manufacturer) {
831 case LPDDR2_MANUFACTURER_SAMSUNG:
833 case LPDDR2_MANUFACTURER_QIMONDA:
835 case LPDDR2_MANUFACTURER_ELPIDA:
837 case LPDDR2_MANUFACTURER_ETRON:
839 case LPDDR2_MANUFACTURER_NANYA:
841 case LPDDR2_MANUFACTURER_HYNIX:
843 case LPDDR2_MANUFACTURER_MOSEL:
845 case LPDDR2_MANUFACTURER_WINBOND:
847 case LPDDR2_MANUFACTURER_ESMT:
849 case LPDDR2_MANUFACTURER_SPANSION:
851 case LPDDR2_MANUFACTURER_SST:
853 case LPDDR2_MANUFACTURER_ZMOS:
855 case LPDDR2_MANUFACTURER_INTEL:
857 case LPDDR2_MANUFACTURER_NUMONYX:
859 case LPDDR2_MANUFACTURER_MICRON:
866 static void display_sdram_details(u32 emif_nr, u32 cs,
867 struct lpddr2_device_details *device)
870 const char *type_str;
871 char density_str[10];
874 debug("EMIF%d CS%d\t", emif_nr, cs);
881 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
882 type_str = get_lpddr2_type(device->type);
884 density = lpddr2_density_2_size_in_mbytes[device->density];
885 if ((density / 1024 * 1024) == density) {
887 sprintf(density_str, "%d GB", density);
889 sprintf(density_str, "%d MB", density);
890 if (mfg_str && type_str)
891 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
894 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
895 struct lpddr2_device_details *lpddr2_device)
899 mr = get_mr(base, cs, LPDDR2_MR0);
901 /* Mode register value bigger than 8 bit */
905 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
910 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
913 /* DNV supported - But DNV is only supported for NVM */
917 mr = get_mr(base, cs, LPDDR2_MR4);
919 /* Mode register value bigger than 8 bit */
923 mr = get_mr(base, cs, LPDDR2_MR5);
925 /* Mode register value bigger than 8 bit */
929 if (!get_lpddr2_manufacturer(mr)) {
930 /* Manufacturer not identified */
933 lpddr2_device->manufacturer = mr;
935 mr = get_mr(base, cs, LPDDR2_MR6);
937 /* Mode register value bigger than 8 bit */
941 mr = get_mr(base, cs, LPDDR2_MR7);
943 /* Mode register value bigger than 8 bit */
947 mr = get_mr(base, cs, LPDDR2_MR8);
949 /* Mode register value bigger than 8 bit */
953 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
954 if (!get_lpddr2_type(temp)) {
958 lpddr2_device->type = temp;
960 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
961 if (temp > LPDDR2_DENSITY_32Gb) {
962 /* Density not supported */
965 lpddr2_device->density = temp;
967 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
968 if (!get_lpddr2_io_width(temp)) {
969 /* IO width unsupported value */
972 lpddr2_device->io_width = temp;
975 * If all the above tests pass we should
976 * have a device on this chip-select
981 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
982 struct lpddr2_device_details *lpddr2_dev_details)
985 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
987 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
989 if (!lpddr2_dev_details)
992 /* Do the minimum init for mode register accesses */
993 if (!running_from_sdram()) {
994 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
995 writel(phy, &emif->emif_ddr_phy_ctrl_1);
998 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1001 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1003 return lpddr2_dev_details;
1005 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1007 static void do_sdram_init(u32 base)
1009 const struct emif_regs *regs;
1010 u32 in_sdram, emif_nr;
1012 debug(">>do_sdram_init() %x\n", base);
1014 in_sdram = running_from_sdram();
1015 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1017 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1018 emif_get_reg_dump(emif_nr, ®s);
1020 debug("EMIF: reg dump not provided\n");
1025 * The user has not provided the register values. We need to
1026 * calculate it based on the timings and the DDR frequency
1028 struct emif_device_details dev_details;
1029 struct emif_regs calculated_regs;
1032 * Get device details:
1033 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1034 * - Obtained from user otherwise
1036 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1037 emif_reset_phy(base);
1038 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1040 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1042 emif_reset_phy(base);
1044 /* Return if no devices on this EMIF */
1045 if (!dev_details.cs0_device_details &&
1046 !dev_details.cs1_device_details) {
1047 emif_sizes[emif_nr - 1] = 0;
1052 emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
1055 * Get device timings:
1056 * - Default timings specified by JESD209-2 if
1057 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1058 * - Obtained from user otherwise
1060 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1061 &dev_details.cs1_device_timings);
1063 /* Calculate the register values */
1064 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1065 regs = &calculated_regs;
1066 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1069 * Initializing the LPDDR2 device can not happen from SDRAM.
1070 * Changing the timing registers in EMIF can happen(going from one
1074 if (omap_revision() != OMAP5432_ES1_0)
1075 lpddr2_init(base, regs);
1077 ddr3_init(base, regs);
1080 /* Write to the shadow registers */
1081 emif_update_timings(base, regs);
1083 debug("<<do_sdram_init() %x\n", base);
1086 void emif_post_init_config(u32 base)
1088 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1089 u32 omap_rev = omap_revision();
1091 if (omap_rev == OMAP5430_ES1_0)
1094 /* reset phy on ES2.0 */
1095 if (omap_rev == OMAP4430_ES2_0)
1096 emif_reset_phy(base);
1098 /* Put EMIF back in smart idle on ES1.0 */
1099 if (omap_rev == OMAP4430_ES1_0)
1100 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1103 void dmm_init(u32 base)
1105 const struct dmm_lisa_map_regs *lisa_map_regs;
1107 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1108 emif_get_dmm_regs(&lisa_map_regs);
1110 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1111 u32 section_cnt, sys_addr;
1112 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1116 sys_addr = CONFIG_SYS_SDRAM_BASE;
1117 emif1_size = emif_sizes[0];
1118 emif2_size = emif_sizes[1];
1119 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1121 if (!emif1_size && !emif2_size)
1124 /* symmetric interleaved section */
1125 if (emif1_size && emif2_size) {
1126 mapped_size = min(emif1_size, emif2_size);
1127 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1128 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1130 section_map |= (sys_addr >> 24) <<
1131 EMIF_SYS_ADDR_SHIFT;
1132 section_map |= get_dmm_section_size_map(mapped_size * 2)
1133 << EMIF_SYS_SIZE_SHIFT;
1134 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1135 emif1_size -= mapped_size;
1136 emif2_size -= mapped_size;
1137 sys_addr += (mapped_size * 2);
1142 * Single EMIF section(we can have a maximum of 1 single EMIF
1143 * section- either EMIF1 or EMIF2 or none, but not both)
1146 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1147 section_map |= get_dmm_section_size_map(emif1_size)
1148 << EMIF_SYS_SIZE_SHIFT;
1150 section_map |= (mapped_size >> 24) <<
1151 EMIF_SDRC_ADDR_SHIFT;
1153 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1157 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1158 section_map |= get_dmm_section_size_map(emif2_size) <<
1159 EMIF_SYS_SIZE_SHIFT;
1161 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1163 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1167 if (section_cnt == 2) {
1168 /* Only 1 section - either symmetric or single EMIF */
1169 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1170 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1171 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1173 /* 2 sections - 1 symmetric, 1 single EMIF */
1174 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1175 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1178 /* TRAP for invalid TILER mappings in section 0 */
1179 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1181 lisa_map_regs = &lis_map_regs_calculated;
1183 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1184 (struct dmm_lisa_map_regs *)base;
1186 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1187 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1188 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1189 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1191 writel(lisa_map_regs->dmm_lisa_map_3,
1192 &hw_lisa_map_regs->dmm_lisa_map_3);
1193 writel(lisa_map_regs->dmm_lisa_map_2,
1194 &hw_lisa_map_regs->dmm_lisa_map_2);
1195 writel(lisa_map_regs->dmm_lisa_map_1,
1196 &hw_lisa_map_regs->dmm_lisa_map_1);
1197 writel(lisa_map_regs->dmm_lisa_map_0,
1198 &hw_lisa_map_regs->dmm_lisa_map_0);
1200 if (omap_revision() >= OMAP4460_ES1_0) {
1202 (struct dmm_lisa_map_regs *)MA_BASE;
1204 writel(lisa_map_regs->dmm_lisa_map_3,
1205 &hw_lisa_map_regs->dmm_lisa_map_3);
1206 writel(lisa_map_regs->dmm_lisa_map_2,
1207 &hw_lisa_map_regs->dmm_lisa_map_2);
1208 writel(lisa_map_regs->dmm_lisa_map_1,
1209 &hw_lisa_map_regs->dmm_lisa_map_1);
1210 writel(lisa_map_regs->dmm_lisa_map_0,
1211 &hw_lisa_map_regs->dmm_lisa_map_0);
1216 * SDRAM initialization:
1217 * SDRAM initialization has two parts:
1218 * 1. Configuring the SDRAM device
1219 * 2. Update the AC timings related parameters in the EMIF module
1220 * (1) should be done only once and should not be done while we are
1221 * running from SDRAM.
1222 * (2) can and should be done more than once if OPP changes.
1223 * Particularly, this may be needed when we boot without SPL and
1224 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1225 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1226 * the frequency. So,
1227 * Doing (1) and (2) makes sense - first time initialization
1228 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1229 * Doing (1) and not (2) doen't make sense
1230 * See do_sdram_init() for the details
1232 void sdram_init(void)
1234 u32 in_sdram, size_prog, size_detect;
1235 u32 omap_rev = omap_revision();
1237 debug(">>sdram_init()\n");
1239 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1242 in_sdram = running_from_sdram();
1243 debug("in_sdram = %d\n", in_sdram);
1246 if (omap_rev != OMAP5432_ES1_0)
1247 bypass_dpll(&prcm->cm_clkmode_dpll_core);
1249 writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
1252 do_sdram_init(EMIF1_BASE);
1253 do_sdram_init(EMIF2_BASE);
1257 emif_post_init_config(EMIF1_BASE);
1258 emif_post_init_config(EMIF2_BASE);
1261 /* for the shadow registers to take effect */
1262 if (omap_rev != OMAP5432_ES1_0)
1265 /* Do some testing after the init */
1267 size_prog = omap_sdram_size();
1268 size_prog = log_2_n_round_down(size_prog);
1269 size_prog = (1 << size_prog);
1271 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1273 /* Compare with the size programmed */
1274 if (size_detect != size_prog) {
1275 printf("SDRAM: identified size not same as expected"
1276 " size identified: %x expected: %x\n",
1280 debug("get_ram_size() successful");
1283 debug("<<sdram_init()\n");