arch/arm/cpu/armv7/omap-common/emif-common.c

   1 /*
   2  * EMIF programming
   3  *
   4  * (C) Copyright 2010
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/emif.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19
  20 static int emif1_enabled = -1, emif2_enabled = -1;
  21
  22 void set_lpmode_selfrefresh(u32 base)
  23 {
  24         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  25         u32 reg;
  26
  27         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  28         reg &= ~EMIF_REG_LP_MODE_MASK;
  29         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  30         reg &= ~EMIF_REG_SR_TIM_MASK;
  31         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  32
  33         /* dummy read for the new SR_TIM to be loaded */
  34         readl(&emif->emif_pwr_mgmt_ctrl);
  35 }
  36
  37 void force_emif_self_refresh()
  38 {
  39         set_lpmode_selfrefresh(EMIF1_BASE);
  40         set_lpmode_selfrefresh(EMIF2_BASE);
  41 }
  42
  43 inline u32 emif_num(u32 base)
  44 {
  45         if (base == EMIF1_BASE)
  46                 return 1;
  47         else if (base == EMIF2_BASE)
  48                 return 2;
  49         else
  50                 return 0;
  51 }
  52
  53 /*
  54  * Get SDRAM type connected to EMIF.
  55  * Assuming similar SDRAM parts are connected to both EMIF's
  56  * which is typically the case. So it is sufficient to get
  57  * SDRAM type from EMIF1.
  58  */
  59 u32 emif_sdram_type()
  60 {
  61         struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  62
  63         return (readl(&emif->emif_sdram_config) &
  64                 EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
  65 }
  66
  67 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  68 {
  69         u32 mr;
  70         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  71
  72         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  73         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  74         if (omap_revision() == OMAP4430_ES2_0)
  75                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  76         else
  77                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  78         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  79               cs, mr_addr, mr);
  80         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  81             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  82             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  83                 return mr & 0xff;
  84         else
  85                 return mr;
  86 }
  87
  88 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  89 {
  90         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  91
  92         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  93         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  94         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  95 }
  96
  97 void emif_reset_phy(u32 base)
  98 {
  99         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 100         u32 iodft;
 101
 102         iodft = readl(&emif->emif_iodft_tlgc);
 103         iodft |= EMIF_REG_RESET_PHY_MASK;
 104         writel(iodft, &emif->emif_iodft_tlgc);
 105 }
 106
 107 static void do_lpddr2_init(u32 base, u32 cs)
 108 {
 109         u32 mr_addr;
 110         const struct lpddr2_mr_regs *mr_regs;
 111
 112         get_lpddr2_mr_regs(&mr_regs);
 113         /* Wait till device auto initialization is complete */
 114         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 115                 ;
 116         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 117         /*
 118          * tZQINIT = 1 us
 119          * Enough loops assuming a maximum of 2GHz
 120          */
 121
 122         sdelay(2000);
 123
 124         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 125         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 126
 127         /*
 128          * Enable refresh along with writing MR2
 129          * Encoding of RL in MR2 is (RL - 2)
 130          */
 131         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 132         set_mr(base, cs, mr_addr, mr_regs->mr2);
 133
 134         if (mr_regs->mr3 > 0)
 135                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 136 }
 137
 138 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 139 {
 140         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 141
 142         /* Not NVM */
 143         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 144
 145         /*
 146          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 147          * when EMIF_SDRAM_CONFIG register is written
 148          */
 149         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 150
 151         /*
 152          * Set the SDRAM_CONFIG and PHY_CTRL for the
 153          * un-locked frequency & default RL
 154          */
 155         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 156         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 157
 158         do_ext_phy_settings(base, regs);
 159
 160         do_lpddr2_init(base, CS0);
 161         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 162                 do_lpddr2_init(base, CS1);
 163
 164         writel(regs->sdram_config, &emif->emif_sdram_config);
 165         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 166
 167         /* Enable refresh now */
 168         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 169
 170         }
 171
 172 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 173 {
 174 }
 175
 176 void emif_update_timings(u32 base, const struct emif_regs *regs)
 177 {
 178         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 179
 180         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 181         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 182         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 183         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 184         if (omap_revision() == OMAP4430_ES1_0) {
 185                 /* ES1 bug EMIF should be in force idle during freq_update */
 186                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 187         } else {
 188                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 189                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 190         }
 191         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 192         writel(regs->zq_config, &emif->emif_zq_config);
 193         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 194         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 195
 196         if ((omap_revision() >= OMAP5430_ES1_0) ||
 197                                 (omap_revision() == DRA752_ES1_0)) {
 198                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 199                         &emif->emif_l3_config);
 200         } else if (omap_revision() >= OMAP4460_ES1_0) {
 201                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 202                         &emif->emif_l3_config);
 203         } else {
 204                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 205                         &emif->emif_l3_config);
 206         }
 207 }
 208
 209 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 210 {
 211         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 212
 213         /* keep sdram in self-refresh */
 214         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 215                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 216         __udelay(130);
 217
 218         /*
 219          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 220          * Invert clock adds an additional half cycle delay on the
 221          * command interface.  The additional half cycle, is usually
 222          * meant to enable leveling in the situation that DQS is later
 223          * than CK on the board.It also helps provide some additional
 224          * margin for leveling.
 225          */
 226         writel(regs->emif_ddr_phy_ctlr_1,
 227                &emif->emif_ddr_phy_ctrl_1);
 228
 229         writel(regs->emif_ddr_phy_ctlr_1,
 230                &emif->emif_ddr_phy_ctrl_1_shdw);
 231         __udelay(130);
 232
 233         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 234                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 235
 236         /* Launch Full leveling */
 237         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 238
 239         /* Wait till full leveling is complete */
 240         readl(&emif->emif_rd_wr_lvl_ctl);
 241               __udelay(130);
 242
 243         /* Read data eye leveling no of samples */
 244         config_data_eye_leveling_samples(base);
 245
 246         /*
 247          * Launch 8 incremental WR_LVL- to compensate for
 248          * PHY limitation.
 249          */
 250         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 251                &emif->emif_rd_wr_lvl_ctl);
 252
 253         __udelay(130);
 254
 255         /* Launch Incremental leveling */
 256         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 257                __udelay(130);
 258 }
 259
 260 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 261 {
 262         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 263
 264         u32 fifo_reg;
 265
 266         fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
 267         writel(fifo_reg | 0x00000100,
 268                &emif->emif_ddr_fifo_misaligned_clear_1);
 269
 270         fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
 271         writel(fifo_reg | 0x00000100,
 272                &emif->emif_ddr_fifo_misaligned_clear_2);
 273
 274         /* Launch Full leveling */
 275         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 276
 277         /* Wait till full leveling is complete */
 278         readl(&emif->emif_rd_wr_lvl_ctl);
 279               __udelay(130);
 280
 281         /* Read data eye leveling no of samples */
 282         config_data_eye_leveling_samples(base);
 283
 284         /*
 285          * Disable leveling. This is because if leveling is kept
 286          * enabled, then PHY triggers a false leveling during
 287          * EMIF-idle scenario which results in wrong delay
 288          * values getting updated. After this the EMIF becomes
 289          * unaccessible. So disable it after the first time
 290          */
 291         writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 292 }
 293
 294 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 295 {
 296         if (is_omap54xx())
 297                 omap5_ddr3_leveling(base, regs);
 298         else
 299                 dra7_ddr3_leveling(base, regs);
 300 }
 301
 302 static void ddr3_init(u32 base, const struct emif_regs *regs)
 303 {
 304         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 305
 306         /*
 307          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 308          * and RL =7. As the default values of the Mode Registers are not
 309          * defined, contents of mode Registers must be fully initialized.
 310          * H/W takes care of this initialization
 311          */
 312         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 313
 314         /* Update timing registers */
 315         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 316         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 317         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 318
 319         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 320         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 321
 322         /*
 323          * The same sequence should work on OMAP5432 as well. But strange that
 324          * it is not working
 325          */
 326         if (omap_revision() == DRA752_ES1_0) {
 327                 do_ext_phy_settings(base, regs);
 328                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 329                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 330         } else {
 331                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 332                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 333                 do_ext_phy_settings(base, regs);
 334         }
 335
 336         /* enable leveling */
 337         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 338
 339         ddr3_leveling(base, regs);
 340 }
 341
 342 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 343 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 344
 345 /*
 346  * Organization and refresh requirements for LPDDR2 devices of different
 347  * types and densities. Derived from JESD209-2 section 2.4
 348  */
 349 const struct lpddr2_addressing addressing_table[] = {
 350         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 351         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 352         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 353         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 354         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 355         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 356         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 357         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 358         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 359         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 360         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 361 };
 362
 363 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 364         8,                      /* 64Mb */
 365         16,                     /* 128Mb */
 366         32,                     /* 256Mb */
 367         64,                     /* 512Mb */
 368         128,                    /* 1Gb   */
 369         256,                    /* 2Gb   */
 370         512,                    /* 4Gb   */
 371         1024,                   /* 8Gb   */
 372         2048,                   /* 16Gb  */
 373         4096                    /* 32Gb  */
 374 };
 375
 376 /*
 377  * Calculate the period of DDR clock from frequency value and set the
 378  * denominator and numerator in global variables for easy access later
 379  */
 380 static void set_ddr_clk_period(u32 freq)
 381 {
 382         /*
 383          * period = 1/freq
 384          * period_in_ns = 10^9/freq
 385          */
 386         *T_num = 1000000000;
 387         *T_den = freq;
 388         cancel_out(T_num, T_den, 200);
 389
 390 }
 391
 392 /*
 393  * Convert time in nano seconds to number of cycles of DDR clock
 394  */
 395 static inline u32 ns_2_cycles(u32 ns)
 396 {
 397         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 398 }
 399
 400 /*
 401  * ns_2_cycles with the difference that the time passed is 2 times the actual
 402  * value(to avoid fractions). The cycles returned is for the original value of
 403  * the timing parameter
 404  */
 405 static inline u32 ns_x2_2_cycles(u32 ns)
 406 {
 407         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 408 }
 409
 410 /*
 411  * Find addressing table index based on the device's type(S2 or S4) and
 412  * density
 413  */
 414 s8 addressing_table_index(u8 type, u8 density, u8 width)
 415 {
 416         u8 index;
 417         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 418                 return -1;
 419
 420         /*
 421          * Look at the way ADDR_TABLE_INDEX* values have been defined
 422          * in emif.h compared to LPDDR2_DENSITY_* values
 423          * The table is layed out in the increasing order of density
 424          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 425          * at the end
 426          */
 427         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 428                 index = ADDR_TABLE_INDEX1GS2;
 429         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 430                 index = ADDR_TABLE_INDEX2GS2;
 431         else
 432                 index = density;
 433
 434         debug("emif: addressing table index %d\n", index);
 435
 436         return index;
 437 }
 438
 439 /*
 440  * Find the the right timing table from the array of timing
 441  * tables of the device using DDR clock frequency
 442  */
 443 static const struct lpddr2_ac_timings *get_timings_table(const struct
 444                         lpddr2_ac_timings const *const *device_timings,
 445                         u32 freq)
 446 {
 447         u32 i, temp, freq_nearest;
 448         const struct lpddr2_ac_timings *timings = 0;
 449
 450         emif_assert(freq <= MAX_LPDDR2_FREQ);
 451         emif_assert(device_timings);
 452
 453         /*
 454          * Start with the maximum allowed frequency - that is always safe
 455          */
 456         freq_nearest = MAX_LPDDR2_FREQ;
 457         /*
 458          * Find the timings table that has the max frequency value:
 459          *   i.  Above or equal to the DDR frequency - safe
 460          *   ii. The lowest that satisfies condition (i) - optimal
 461          */
 462         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 463                 temp = device_timings[i]->max_freq;
 464                 if ((temp >= freq) && (temp <= freq_nearest)) {
 465                         freq_nearest = temp;
 466                         timings = device_timings[i];
 467                 }
 468         }
 469         debug("emif: timings table: %d\n", freq_nearest);
 470         return timings;
 471 }
 472
 473 /*
 474  * Finds the value of emif_sdram_config_reg
 475  * All parameters are programmed based on the device on CS0.
 476  * If there is a device on CS1, it will be same as that on CS0 or
 477  * it will be NVM. We don't support NVM yet.
 478  * If cs1_device pointer is NULL it is assumed that there is no device
 479  * on CS1
 480  */
 481 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 482                                 const struct lpddr2_device_details *cs1_device,
 483                                 const struct lpddr2_addressing *addressing,
 484                                 u8 RL)
 485 {
 486         u32 config_reg = 0;
 487
 488         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 489         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 490                         EMIF_REG_IBANK_POS_SHIFT;
 491
 492         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 493
 494         config_reg |= RL << EMIF_REG_CL_SHIFT;
 495
 496         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 497                         EMIF_REG_ROWSIZE_SHIFT;
 498
 499         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 500
 501         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 502                         EMIF_REG_EBANK_SHIFT;
 503
 504         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 505                         EMIF_REG_PAGESIZE_SHIFT;
 506
 507         return config_reg;
 508 }
 509
 510 static u32 get_sdram_ref_ctrl(u32 freq,
 511                               const struct lpddr2_addressing *addressing)
 512 {
 513         u32 ref_ctrl = 0, val = 0, freq_khz;
 514         freq_khz = freq / 1000;
 515         /*
 516          * refresh rate to be set is 'tREFI * freq in MHz
 517          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 518          */
 519         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 520         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 521
 522         return ref_ctrl;
 523 }
 524
 525 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 526                                const struct lpddr2_min_tck *min_tck,
 527                                const struct lpddr2_addressing *addressing)
 528 {
 529         u32 tim1 = 0, val = 0;
 530         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 531         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 532
 533         if (addressing->num_banks == BANKS8)
 534                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 535                                                         (4 * (*T_num)) - 1;
 536         else
 537                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 538
 539         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 540
 541         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 542         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 543
 544         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 545         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 546
 547         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 548         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 549
 550         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 551         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 552
 553         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 554         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 555
 556         return tim1;
 557 }
 558
 559 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 560                                const struct lpddr2_min_tck *min_tck)
 561 {
 562         u32 tim2 = 0, val = 0;
 563         val = max(min_tck->tCKE, timings->tCKE) - 1;
 564         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 565
 566         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 567         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 568
 569         /*
 570          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 571          * same value
 572          */
 573         val = ns_2_cycles(timings->tXSR) - 1;
 574         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 575         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 576
 577         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 578         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 579
 580         return tim2;
 581 }
 582
 583 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 584                                const struct lpddr2_min_tck *min_tck,
 585                                const struct lpddr2_addressing *addressing)
 586 {
 587         u32 tim3 = 0, val = 0;
 588         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 589         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 590
 591         val = ns_2_cycles(timings->tRFCab) - 1;
 592         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 593
 594         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 595         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 596
 597         val = ns_2_cycles(timings->tZQCS) - 1;
 598         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 599
 600         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 601         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 602
 603         return tim3;
 604 }
 605
 606 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 607                              const struct lpddr2_addressing *addressing,
 608                              u8 volt_ramp)
 609 {
 610         u32 zq = 0, val = 0;
 611         if (volt_ramp)
 612                 val =
 613                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 614                     addressing->t_REFI_us_x10;
 615         else
 616                 val =
 617                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 618                     addressing->t_REFI_us_x10;
 619         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 620
 621         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 622
 623         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 624
 625         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 626
 627         /*
 628          * Assuming that two chipselects have a single calibration resistor
 629          * If there are indeed two calibration resistors, then this flag should
 630          * be enabled to take advantage of dual calibration feature.
 631          * This data should ideally come from board files. But considering
 632          * that none of the boards today have calibration resistors per CS,
 633          * it would be an unnecessary overhead.
 634          */
 635         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 636
 637         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 638
 639         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 640
 641         return zq;
 642 }
 643
 644 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 645                                  const struct lpddr2_addressing *addressing,
 646                                  u8 is_derated)
 647 {
 648         u32 alert = 0, interval;
 649         interval =
 650             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 651         if (is_derated)
 652                 interval *= 4;
 653         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 654
 655         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 656
 657         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 658
 659         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 660
 661         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 662
 663         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 664
 665         return alert;
 666 }
 667
 668 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 669 {
 670         u32 idle = 0, val = 0;
 671         if (volt_ramp)
 672                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 673         else
 674                 /*Maximum value in normal conditions - suggested by hw team */
 675                 val = 0x1FF;
 676         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 677
 678         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 679
 680         return idle;
 681 }
 682
 683 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 684 {
 685         u32 phy = 0, val = 0;
 686
 687         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 688
 689         if (freq <= 100000000)
 690                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 691         else if (freq <= 200000000)
 692                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 693         else
 694                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 695         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 696
 697         /* Other fields are constant magic values. Hardcode them together */
 698         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 699                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 700
 701         return phy;
 702 }
 703
 704 static u32 get_emif_mem_size(u32 base)
 705 {
 706         u32 size_mbytes = 0, temp;
 707         struct emif_device_details dev_details;
 708         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 709         u32 emif_nr = emif_num(base);
 710
 711         emif_reset_phy(base);
 712         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 713                                                 &cs0_dev_details);
 714         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 715                                                 &cs1_dev_details);
 716         emif_reset_phy(base);
 717
 718         if (dev_details.cs0_device_details) {
 719                 temp = dev_details.cs0_device_details->density;
 720                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 721         }
 722
 723         if (dev_details.cs1_device_details) {
 724                 temp = dev_details.cs1_device_details->density;
 725                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 726         }
 727         /* convert to bytes */
 728         return size_mbytes << 20;
 729 }
 730
 731 /* Gets the encoding corresponding to a given DMM section size */
 732 u32 get_dmm_section_size_map(u32 section_size)
 733 {
 734         /*
 735          * Section size mapping:
 736          * 0x0: 16-MiB section
 737          * 0x1: 32-MiB section
 738          * 0x2: 64-MiB section
 739          * 0x3: 128-MiB section
 740          * 0x4: 256-MiB section
 741          * 0x5: 512-MiB section
 742          * 0x6: 1-GiB section
 743          * 0x7: 2-GiB section
 744          */
 745         section_size >>= 24; /* divide by 16 MB */
 746         return log_2_n_round_down(section_size);
 747 }
 748
 749 static void emif_calculate_regs(
 750                 const struct emif_device_details *emif_dev_details,
 751                 u32 freq, struct emif_regs *regs)
 752 {
 753         u32 temp, sys_freq;
 754         const struct lpddr2_addressing *addressing;
 755         const struct lpddr2_ac_timings *timings;
 756         const struct lpddr2_min_tck *min_tck;
 757         const struct lpddr2_device_details *cs0_dev_details =
 758                                         emif_dev_details->cs0_device_details;
 759         const struct lpddr2_device_details *cs1_dev_details =
 760                                         emif_dev_details->cs1_device_details;
 761         const struct lpddr2_device_timings *cs0_dev_timings =
 762                                         emif_dev_details->cs0_device_timings;
 763
 764         emif_assert(emif_dev_details);
 765         emif_assert(regs);
 766         /*
 767          * You can not have a device on CS1 without one on CS0
 768          * So configuring EMIF without a device on CS0 doesn't
 769          * make sense
 770          */
 771         emif_assert(cs0_dev_details);
 772         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 773         /*
 774          * If there is a device on CS1 it should be same type as CS0
 775          * (or NVM. But NVM is not supported in this driver yet)
 776          */
 777         emif_assert((cs1_dev_details == NULL) ||
 778                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 779                     (cs0_dev_details->type == cs1_dev_details->type));
 780         emif_assert(freq <= MAX_LPDDR2_FREQ);
 781
 782         set_ddr_clk_period(freq);
 783
 784         /*
 785          * The device on CS0 is used for all timing calculations
 786          * There is only one set of registers for timings per EMIF. So, if the
 787          * second CS(CS1) has a device, it should have the same timings as the
 788          * device on CS0
 789          */
 790         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 791         emif_assert(timings);
 792         min_tck = cs0_dev_timings->min_tck;
 793
 794         temp = addressing_table_index(cs0_dev_details->type,
 795                                       cs0_dev_details->density,
 796                                       cs0_dev_details->io_width);
 797
 798         emif_assert((temp >= 0));
 799         addressing = &(addressing_table[temp]);
 800         emif_assert(addressing);
 801
 802         sys_freq = get_sys_clk_freq();
 803
 804         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 805                                                         cs1_dev_details,
 806                                                         addressing, RL_BOOT);
 807
 808         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 809                                                 cs1_dev_details,
 810                                                 addressing, RL_FINAL);
 811
 812         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 813
 814         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 815
 816         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 817
 818         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 819
 820         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 821
 822         regs->temp_alert_config =
 823             get_temp_alert_config(cs1_dev_details, addressing, 0);
 824
 825         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 826                                             LPDDR2_VOLTAGE_STABLE);
 827
 828         regs->emif_ddr_phy_ctlr_1_init =
 829                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 830
 831         regs->emif_ddr_phy_ctlr_1 =
 832                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
 833
 834         regs->freq = freq;
 835
 836         print_timing_reg(regs->sdram_config_init);
 837         print_timing_reg(regs->sdram_config);
 838         print_timing_reg(regs->ref_ctrl);
 839         print_timing_reg(regs->sdram_tim1);
 840         print_timing_reg(regs->sdram_tim2);
 841         print_timing_reg(regs->sdram_tim3);
 842         print_timing_reg(regs->read_idle_ctrl);
 843         print_timing_reg(regs->temp_alert_config);
 844         print_timing_reg(regs->zq_config);
 845         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
 846         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
 847 }
 848 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 849
 850 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 851 const char *get_lpddr2_type(u8 type_id)
 852 {
 853         switch (type_id) {
 854         case LPDDR2_TYPE_S4:
 855                 return "LPDDR2-S4";
 856         case LPDDR2_TYPE_S2:
 857                 return "LPDDR2-S2";
 858         default:
 859                 return NULL;
 860         }
 861 }
 862
 863 const char *get_lpddr2_io_width(u8 width_id)
 864 {
 865         switch (width_id) {
 866         case LPDDR2_IO_WIDTH_8:
 867                 return "x8";
 868         case LPDDR2_IO_WIDTH_16:
 869                 return "x16";
 870         case LPDDR2_IO_WIDTH_32:
 871                 return "x32";
 872         default:
 873                 return NULL;
 874         }
 875 }
 876
 877 const char *get_lpddr2_manufacturer(u32 manufacturer)
 878 {
 879         switch (manufacturer) {
 880         case LPDDR2_MANUFACTURER_SAMSUNG:
 881                 return "Samsung";
 882         case LPDDR2_MANUFACTURER_QIMONDA:
 883                 return "Qimonda";
 884         case LPDDR2_MANUFACTURER_ELPIDA:
 885                 return "Elpida";
 886         case LPDDR2_MANUFACTURER_ETRON:
 887                 return "Etron";
 888         case LPDDR2_MANUFACTURER_NANYA:
 889                 return "Nanya";
 890         case LPDDR2_MANUFACTURER_HYNIX:
 891                 return "Hynix";
 892         case LPDDR2_MANUFACTURER_MOSEL:
 893                 return "Mosel";
 894         case LPDDR2_MANUFACTURER_WINBOND:
 895                 return "Winbond";
 896         case LPDDR2_MANUFACTURER_ESMT:
 897                 return "ESMT";
 898         case LPDDR2_MANUFACTURER_SPANSION:
 899                 return "Spansion";
 900         case LPDDR2_MANUFACTURER_SST:
 901                 return "SST";
 902         case LPDDR2_MANUFACTURER_ZMOS:
 903                 return "ZMOS";
 904         case LPDDR2_MANUFACTURER_INTEL:
 905                 return "Intel";
 906         case LPDDR2_MANUFACTURER_NUMONYX:
 907                 return "Numonyx";
 908         case LPDDR2_MANUFACTURER_MICRON:
 909                 return "Micron";
 910         default:
 911                 return NULL;
 912         }
 913 }
 914
 915 static void display_sdram_details(u32 emif_nr, u32 cs,
 916                                   struct lpddr2_device_details *device)
 917 {
 918         const char *mfg_str;
 919         const char *type_str;
 920         char density_str[10];
 921         u32 density;
 922
 923         debug("EMIF%d CS%d\t", emif_nr, cs);
 924
 925         if (!device) {
 926                 debug("None\n");
 927                 return;
 928         }
 929
 930         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
 931         type_str = get_lpddr2_type(device->type);
 932
 933         density = lpddr2_density_2_size_in_mbytes[device->density];
 934         if ((density / 1024 * 1024) == density) {
 935                 density /= 1024;
 936                 sprintf(density_str, "%d GB", density);
 937         } else
 938                 sprintf(density_str, "%d MB", density);
 939         if (mfg_str && type_str)
 940                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
 941 }
 942
 943 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
 944                                   struct lpddr2_device_details *lpddr2_device)
 945 {
 946         u32 mr = 0, temp;
 947
 948         mr = get_mr(base, cs, LPDDR2_MR0);
 949         if (mr > 0xFF) {
 950                 /* Mode register value bigger than 8 bit */
 951                 return 0;
 952         }
 953
 954         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
 955         if (temp) {
 956                 /* Not SDRAM */
 957                 return 0;
 958         }
 959         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
 960
 961         if (temp) {
 962                 /* DNV supported - But DNV is only supported for NVM */
 963                 return 0;
 964         }
 965
 966         mr = get_mr(base, cs, LPDDR2_MR4);
 967         if (mr > 0xFF) {
 968                 /* Mode register value bigger than 8 bit */
 969                 return 0;
 970         }
 971
 972         mr = get_mr(base, cs, LPDDR2_MR5);
 973         if (mr > 0xFF) {
 974                 /* Mode register value bigger than 8 bit */
 975                 return 0;
 976         }
 977
 978         if (!get_lpddr2_manufacturer(mr)) {
 979                 /* Manufacturer not identified */
 980                 return 0;
 981         }
 982         lpddr2_device->manufacturer = mr;
 983
 984         mr = get_mr(base, cs, LPDDR2_MR6);
 985         if (mr >= 0xFF) {
 986                 /* Mode register value bigger than 8 bit */
 987                 return 0;
 988         }
 989
 990         mr = get_mr(base, cs, LPDDR2_MR7);
 991         if (mr >= 0xFF) {
 992                 /* Mode register value bigger than 8 bit */
 993                 return 0;
 994         }
 995
 996         mr = get_mr(base, cs, LPDDR2_MR8);
 997         if (mr >= 0xFF) {
 998                 /* Mode register value bigger than 8 bit */
 999                 return 0;
1000         }
1001
1002         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
1003         if (!get_lpddr2_type(temp)) {
1004                 /* Not SDRAM */
1005                 return 0;
1006         }
1007         lpddr2_device->type = temp;
1008
1009         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
1010         if (temp > LPDDR2_DENSITY_32Gb) {
1011                 /* Density not supported */
1012                 return 0;
1013         }
1014         lpddr2_device->density = temp;
1015
1016         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1017         if (!get_lpddr2_io_width(temp)) {
1018                 /* IO width unsupported value */
1019                 return 0;
1020         }
1021         lpddr2_device->io_width = temp;
1022
1023         /*
1024          * If all the above tests pass we should
1025          * have a device on this chip-select
1026          */
1027         return 1;
1028 }
1029
1030 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1031                         struct lpddr2_device_details *lpddr2_dev_details)
1032 {
1033         u32 phy;
1034         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1035
1036         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1037
1038         if (!lpddr2_dev_details)
1039                 return NULL;
1040
1041         /* Do the minimum init for mode register accesses */
1042         if (!(running_from_sdram() || warm_reset())) {
1043                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1044                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1045         }
1046
1047         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1048                 return NULL;
1049
1050         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1051
1052         return lpddr2_dev_details;
1053 }
1054 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1055
1056 static void do_sdram_init(u32 base)
1057 {
1058         const struct emif_regs *regs;
1059         u32 in_sdram, emif_nr;
1060
1061         debug(">>do_sdram_init() %x\n", base);
1062
1063         in_sdram = running_from_sdram();
1064         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1065
1066 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1067         emif_get_reg_dump(emif_nr, &regs);
1068         if (!regs) {
1069                 debug("EMIF: reg dump not provided\n");
1070                 return;
1071         }
1072 #else
1073         /*
1074          * The user has not provided the register values. We need to
1075          * calculate it based on the timings and the DDR frequency
1076          */
1077         struct emif_device_details dev_details;
1078         struct emif_regs calculated_regs;
1079
1080         /*
1081          * Get device details:
1082          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1083          * - Obtained from user otherwise
1084          */
1085         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1086         emif_reset_phy(base);
1087         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1088                                                 &cs0_dev_details);
1089         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1090                                                 &cs1_dev_details);
1091         emif_reset_phy(base);
1092
1093         /* Return if no devices on this EMIF */
1094         if (!dev_details.cs0_device_details &&
1095             !dev_details.cs1_device_details) {
1096                 return;
1097         }
1098
1099         /*
1100          * Get device timings:
1101          * - Default timings specified by JESD209-2 if
1102          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1103          * - Obtained from user otherwise
1104          */
1105         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1106                                 &dev_details.cs1_device_timings);
1107
1108         /* Calculate the register values */
1109         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1110         regs = &calculated_regs;
1111 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1112
1113         /*
1114          * Initializing the LPDDR2 device can not happen from SDRAM.
1115          * Changing the timing registers in EMIF can happen(going from one
1116          * OPP to another)
1117          */
1118         if (!(in_sdram || warm_reset())) {
1119                 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1120                         lpddr2_init(base, regs);
1121                 else
1122                         ddr3_init(base, regs);
1123         }
1124         if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1125                 set_lpmode_selfrefresh(base);
1126                 emif_reset_phy(base);
1127                 ddr3_leveling(base, regs);
1128         }
1129
1130         /* Write to the shadow registers */
1131         emif_update_timings(base, regs);
1132
1133         debug("<<do_sdram_init() %x\n", base);
1134 }
1135
1136 void emif_post_init_config(u32 base)
1137 {
1138         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1139         u32 omap_rev = omap_revision();
1140
1141         /* reset phy on ES2.0 */
1142         if (omap_rev == OMAP4430_ES2_0)
1143                 emif_reset_phy(base);
1144
1145         /* Put EMIF back in smart idle on ES1.0 */
1146         if (omap_rev == OMAP4430_ES1_0)
1147                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1148 }
1149
1150 void dmm_init(u32 base)
1151 {
1152         const struct dmm_lisa_map_regs *lisa_map_regs;
1153         u32 i, section, valid;
1154
1155 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1156         emif_get_dmm_regs(&lisa_map_regs);
1157 #else
1158         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1159         u32 section_cnt, sys_addr;
1160         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1161
1162         mapped_size = 0;
1163         section_cnt = 3;
1164         sys_addr = CONFIG_SYS_SDRAM_BASE;
1165         emif1_size = get_emif_mem_size(EMIF1_BASE);
1166         emif2_size = get_emif_mem_size(EMIF2_BASE);
1167         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1168
1169         if (!emif1_size && !emif2_size)
1170                 return;
1171
1172         /* symmetric interleaved section */
1173         if (emif1_size && emif2_size) {
1174                 mapped_size = min(emif1_size, emif2_size);
1175                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1176                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1177                 /* only MSB */
1178                 section_map |= (sys_addr >> 24) <<
1179                                 EMIF_SYS_ADDR_SHIFT;
1180                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1181                                 << EMIF_SYS_SIZE_SHIFT;
1182                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1183                 emif1_size -= mapped_size;
1184                 emif2_size -= mapped_size;
1185                 sys_addr += (mapped_size * 2);
1186                 section_cnt--;
1187         }
1188
1189         /*
1190          * Single EMIF section(we can have a maximum of 1 single EMIF
1191          * section- either EMIF1 or EMIF2 or none, but not both)
1192          */
1193         if (emif1_size) {
1194                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1195                 section_map |= get_dmm_section_size_map(emif1_size)
1196                                 << EMIF_SYS_SIZE_SHIFT;
1197                 /* only MSB */
1198                 section_map |= (mapped_size >> 24) <<
1199                                 EMIF_SDRC_ADDR_SHIFT;
1200                 /* only MSB */
1201                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1202                 section_cnt--;
1203         }
1204         if (emif2_size) {
1205                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1206                 section_map |= get_dmm_section_size_map(emif2_size) <<
1207                                 EMIF_SYS_SIZE_SHIFT;
1208                 /* only MSB */
1209                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1210                 /* only MSB */
1211                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1212                 section_cnt--;
1213         }
1214
1215         if (section_cnt == 2) {
1216                 /* Only 1 section - either symmetric or single EMIF */
1217                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1218                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1219                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1220         } else {
1221                 /* 2 sections - 1 symmetric, 1 single EMIF */
1222                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1223                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1224         }
1225
1226         /* TRAP for invalid TILER mappings in section 0 */
1227         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1228
1229         if (omap_revision() >= OMAP4460_ES1_0)
1230                 lis_map_regs_calculated.is_ma_present = 1;
1231
1232         lisa_map_regs = &lis_map_regs_calculated;
1233 #endif
1234         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1235             (struct dmm_lisa_map_regs *)base;
1236
1237         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1238         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1239         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1240         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1241
1242         writel(lisa_map_regs->dmm_lisa_map_3,
1243                 &hw_lisa_map_regs->dmm_lisa_map_3);
1244         writel(lisa_map_regs->dmm_lisa_map_2,
1245                 &hw_lisa_map_regs->dmm_lisa_map_2);
1246         writel(lisa_map_regs->dmm_lisa_map_1,
1247                 &hw_lisa_map_regs->dmm_lisa_map_1);
1248         writel(lisa_map_regs->dmm_lisa_map_0,
1249                 &hw_lisa_map_regs->dmm_lisa_map_0);
1250
1251         if (lisa_map_regs->is_ma_present) {
1252                 hw_lisa_map_regs =
1253                     (struct dmm_lisa_map_regs *)MA_BASE;
1254
1255                 writel(lisa_map_regs->dmm_lisa_map_3,
1256                         &hw_lisa_map_regs->dmm_lisa_map_3);
1257                 writel(lisa_map_regs->dmm_lisa_map_2,
1258                         &hw_lisa_map_regs->dmm_lisa_map_2);
1259                 writel(lisa_map_regs->dmm_lisa_map_1,
1260                         &hw_lisa_map_regs->dmm_lisa_map_1);
1261                 writel(lisa_map_regs->dmm_lisa_map_0,
1262                         &hw_lisa_map_regs->dmm_lisa_map_0);
1263         }
1264
1265         /*
1266          * EMIF should be configured only when
1267          * memory is mapped on it. Using emif1_enabled
1268          * and emif2_enabled variables for this.
1269          */
1270         emif1_enabled = 0;
1271         emif2_enabled = 0;
1272         for (i = 0; i < 4; i++) {
1273                 section = __raw_readl(DMM_BASE + i*4);
1274                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1275                         (EMIF_SDRC_MAP_SHIFT);
1276                 if (valid == 3) {
1277                         emif1_enabled = 1;
1278                         emif2_enabled = 1;
1279                         break;
1280                 } else if (valid == 1) {
1281                         emif1_enabled = 1;
1282                 } else if (valid == 2) {
1283                         emif2_enabled = 1;
1284                 }
1285         }
1286
1287 }
1288
1289 static void do_bug0039_workaround(u32 base)
1290 {
1291         u32 val, i, clkctrl;
1292         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1293         const struct read_write_regs *bug_00339_regs;
1294         u32 iterations;
1295         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1296         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1297
1298         if (is_dra7xx())
1299                 phy_status_base++;
1300
1301         bug_00339_regs = get_bug_regs(&iterations);
1302
1303         /* Put EMIF in to idle */
1304         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1305         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1306
1307         /* Copy the phy status registers in to phy ctrl shadow registers */
1308         for (i = 0; i < iterations; i++) {
1309                 val = __raw_readl(phy_status_base +
1310                                   bug_00339_regs[i].read_reg - 1);
1311
1312                 __raw_writel(val, phy_ctrl_base +
1313                              ((bug_00339_regs[i].write_reg - 1) << 1));
1314
1315                 __raw_writel(val, phy_ctrl_base +
1316                              (bug_00339_regs[i].write_reg << 1) - 1);
1317         }
1318
1319         /* Disable leveling */
1320         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1321
1322         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1323 }
1324
1325 /*
1326  * SDRAM initialization:
1327  * SDRAM initialization has two parts:
1328  * 1. Configuring the SDRAM device
1329  * 2. Update the AC timings related parameters in the EMIF module
1330  * (1) should be done only once and should not be done while we are
1331  * running from SDRAM.
1332  * (2) can and should be done more than once if OPP changes.
1333  * Particularly, this may be needed when we boot without SPL and
1334  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1335  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1336  * the frequency. So,
1337  * Doing (1) and (2) makes sense - first time initialization
1338  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1339  * Doing (1) and not (2) doen't make sense
1340  * See do_sdram_init() for the details
1341  */
1342 void sdram_init(void)
1343 {
1344         u32 in_sdram, size_prog, size_detect;
1345         u32 sdram_type = emif_sdram_type();
1346
1347         debug(">>sdram_init()\n");
1348
1349         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1350                 return;
1351
1352         in_sdram = running_from_sdram();
1353         debug("in_sdram = %d\n", in_sdram);
1354
1355         if (!in_sdram) {
1356                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1357                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1358                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1359                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1360         }
1361
1362         if (!in_sdram)
1363                 dmm_init(DMM_BASE);
1364
1365         if (emif1_enabled)
1366                 do_sdram_init(EMIF1_BASE);
1367
1368         if (emif2_enabled)
1369                 do_sdram_init(EMIF2_BASE);
1370
1371         if (!(in_sdram || warm_reset())) {
1372                 if (emif1_enabled)
1373                         emif_post_init_config(EMIF1_BASE);
1374                 if (emif2_enabled)
1375                         emif_post_init_config(EMIF2_BASE);
1376         }
1377
1378         /* for the shadow registers to take effect */
1379         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1380                 freq_update_core();
1381
1382         /* Do some testing after the init */
1383         if (!in_sdram) {
1384                 size_prog = omap_sdram_size();
1385                 size_prog = log_2_n_round_down(size_prog);
1386                 size_prog = (1 << size_prog);
1387
1388                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1389                                                 size_prog);
1390                 /* Compare with the size programmed */
1391                 if (size_detect != size_prog) {
1392                         printf("SDRAM: identified size not same as expected"
1393                                 " size identified: %x expected: %x\n",
1394                                 size_detect,
1395                                 size_prog);
1396                 } else
1397                         debug("get_ram_size() successful");
1398         }
1399
1400         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1401             (!in_sdram && !warm_reset())) {
1402                 do_bug0039_workaround(EMIF1_BASE);
1403                 do_bug0039_workaround(EMIF2_BASE);
1404         }
1405
1406         debug("<<sdram_init()\n");
1407 }