3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
41 #ifndef CONFIG_SPL_BUILD
43 * printing to console doesn't work unless
44 * this code is executed from SPL
46 #define printf(fmt, args...)
50 const u32 sys_clk_array[8] = {
51 12000000, /* 12 MHz */
52 13000000, /* 13 MHz */
53 16800000, /* 16.8 MHz */
54 19200000, /* 19.2 MHz */
55 26000000, /* 26 MHz */
56 27000000, /* 27 MHz */
57 38400000, /* 38.4 MHz */
60 static inline u32 __get_sys_clk_index(void)
64 * For ES1 the ROM code calibration of sys clock is not reliable
65 * due to hw issue. So, use hard-coded value. If this value is not
66 * correct for any board over-ride this function in board file
67 * From ES2.0 onwards you will get this information from
70 if (omap_revision() == OMAP4430_ES1_0)
71 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
73 /* SYS_CLKSEL - 1 to match the dpll param array indices */
74 ind = (readl((*prcm)->cm_sys_clksel) &
75 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
80 u32 get_sys_clk_index(void)
81 __attribute__ ((weak, alias("__get_sys_clk_index")));
83 u32 get_sys_clk_freq(void)
85 u8 index = get_sys_clk_index();
86 return sys_clk_array[index];
89 void setup_post_dividers(u32 const base, const struct dpll_params *params)
91 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
93 /* Setup post-dividers */
95 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
97 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
98 if (params->m4_h11 >= 0)
99 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
100 if (params->m5_h12 >= 0)
101 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
102 if (params->m6_h13 >= 0)
103 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
104 if (params->m7_h14 >= 0)
105 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
106 if (params->h21 >= 0)
107 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
108 if (params->h22 >= 0)
109 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
110 if (params->h23 >= 0)
111 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
112 if (params->h24 >= 0)
113 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
116 static inline void do_bypass_dpll(u32 const base)
118 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
120 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
121 CM_CLKMODE_DPLL_DPLL_EN_MASK,
122 DPLL_EN_FAST_RELOCK_BYPASS <<
123 CM_CLKMODE_DPLL_EN_SHIFT);
126 static inline void wait_for_bypass(u32 const base)
128 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
130 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
132 printf("Bypassing DPLL failed %x\n", base);
136 static inline void do_lock_dpll(u32 const base)
138 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
140 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
141 CM_CLKMODE_DPLL_DPLL_EN_MASK,
142 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
145 static inline void wait_for_lock(u32 const base)
147 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
149 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
150 &dpll_regs->cm_idlest_dpll, LDELAY)) {
151 printf("DPLL locking failed for %x\n", base);
156 inline u32 check_for_lock(u32 const base)
158 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
159 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
164 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
166 u32 sysclk_ind = get_sys_clk_index();
167 return &dpll_data->mpu[sysclk_ind];
170 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
172 u32 sysclk_ind = get_sys_clk_index();
173 return &dpll_data->core[sysclk_ind];
176 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
178 u32 sysclk_ind = get_sys_clk_index();
179 return &dpll_data->per[sysclk_ind];
182 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
184 u32 sysclk_ind = get_sys_clk_index();
185 return &dpll_data->iva[sysclk_ind];
188 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
190 u32 sysclk_ind = get_sys_clk_index();
191 return &dpll_data->usb[sysclk_ind];
194 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
196 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
197 u32 sysclk_ind = get_sys_clk_index();
198 return &dpll_data->abe[sysclk_ind];
200 return dpll_data->abe;
204 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
208 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
210 temp = readl(&dpll_regs->cm_clksel_dpll);
212 if (check_for_lock(base)) {
214 * The Dpll has already been locked by rom code using CH.
215 * Check if M,N are matching with Ideal nominal opp values.
216 * If matches, skip the rest otherwise relock.
218 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
219 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
220 if ((M != (params->m)) || (N != (params->n))) {
221 debug("\n %s Dpll locked, but not for ideal M = %d,"
222 "N = %d values, current values are M = %d,"
223 "N= %d" , dpll, params->m, params->n,
226 /* Dpll locked with ideal values for nominal opps. */
227 debug("\n %s Dpll already locked with ideal"
228 "nominal opp values", dpll);
229 goto setup_post_dividers;
236 temp &= ~CM_CLKSEL_DPLL_M_MASK;
237 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
239 temp &= ~CM_CLKSEL_DPLL_N_MASK;
240 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
242 writel(temp, &dpll_regs->cm_clksel_dpll);
249 setup_post_dividers(base, params);
251 /* Wait till the DPLL locks */
256 u32 omap_ddr_clk(void)
258 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
259 const struct dpll_params *core_dpll_params;
261 omap_rev = omap_revision();
262 sys_clk_khz = get_sys_clk_freq() / 1000;
264 core_dpll_params = get_core_dpll_params(*dplls_data);
266 debug("sys_clk %d\n ", sys_clk_khz * 1000);
268 /* Find Core DPLL locked frequency first */
269 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
270 (core_dpll_params->n + 1);
272 if (omap_rev < OMAP5430_ES1_0) {
274 * DDR frequency is PHY_ROOT_CLK/2
275 * PHY_ROOT_CLK = Fdpll/2/M2
280 * DDR frequency is PHY_ROOT_CLK
281 * PHY_ROOT_CLK = Fdpll/2/M2
286 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
287 ddr_clk *= 1000; /* convert to Hz */
288 debug("ddr_clk %d\n ", ddr_clk);
296 * Resulting MPU frequencies:
297 * 4430 ES1.0 : 600 MHz
298 * 4430 ES2.x : 792 MHz (OPP Turbo)
299 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
301 void configure_mpu_dpll(void)
303 const struct dpll_params *params;
304 struct dpll_regs *mpu_dpll_regs;
306 omap_rev = omap_revision();
309 * DCC and clock divider settings for 4460.
310 * DCC is required, if more than a certain frequency is required.
314 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
316 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
317 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
318 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
319 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
320 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
321 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
322 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
323 CM_CLKSEL_DCC_EN_MASK);
326 params = get_mpu_dpll_params(*dplls_data);
328 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
329 debug("MPU DPLL locked\n");
332 #ifdef CONFIG_USB_EHCI_OMAP
333 static void setup_usb_dpll(void)
335 const struct dpll_params *params;
336 u32 sys_clk_khz, sd_div, num, den;
338 sys_clk_khz = get_sys_clk_freq() / 1000;
341 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
342 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
343 * - where CLKINP is sys_clk in MHz
344 * Use CLKINP in KHz and adjust the denominator accordingly so
345 * that we have enough accuracy and at the same time no overflow
347 params = get_usb_dpll_params(*dplls_data);
348 num = params->m * sys_clk_khz;
349 den = (params->n + 1) * 250 * 1000;
352 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
353 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
354 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
356 /* Now setup the dpll with the regular function */
357 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
361 static void setup_dplls(void)
364 const struct dpll_params *params;
366 debug("setup_dplls\n");
369 params = get_core_dpll_params(*dplls_data); /* default - safest */
371 * Do not lock the core DPLL now. Just set it up.
372 * Core DPLL will be locked after setting up EMIF
373 * using the FREQ_UPDATE method(freq_update_core())
375 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
376 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
377 DPLL_NO_LOCK, "core");
379 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
381 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
382 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
383 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
384 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
385 writel(temp, (*prcm)->cm_clksel_core);
386 debug("Core DPLL configured\n");
389 params = get_per_dpll_params(*dplls_data);
390 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
391 params, DPLL_LOCK, "per");
392 debug("PER DPLL locked\n");
395 configure_mpu_dpll();
397 #ifdef CONFIG_USB_EHCI_OMAP
402 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
403 static void setup_non_essential_dplls(void)
406 const struct dpll_params *params;
409 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
410 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
412 params = get_iva_dpll_params(*dplls_data);
413 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
415 /* Configure ABE dpll */
416 params = get_abe_dpll_params(*dplls_data);
417 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
418 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
420 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
422 * We need to enable some additional options to achieve
423 * 196.608MHz from 32768 Hz
425 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
426 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
427 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
428 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
429 CM_CLKMODE_DPLL_REGM4XEN_MASK);
430 /* Spend 4 REFCLK cycles at each stage */
431 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
432 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
433 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
436 /* Select the right reference clk */
437 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
438 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
439 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
441 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
445 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
449 volt_offset -= pmic->base_offset;
451 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
454 * Offset codes 1-6 all give the base voltage in Palmas
455 * Offset code 0 switches OFF the SMPS
457 return offset_code + pmic->start_code;
460 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
463 u32 offset = volt_mv;
466 /* See if we can first get the GPIO if needed */
468 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
471 printf("%s: gpio %d request failed %d\n", __func__,
476 /* Pull the GPIO low to select SET0 register, while we program SET1 */
478 gpio_direction_output(pmic->gpio, 0);
480 /* convert to uV for better accuracy in the calculations */
483 offset_code = get_offset_code(offset, pmic);
485 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
488 if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
489 vcore_reg, offset_code))
490 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
493 gpio_direction_output(pmic->gpio, 1);
497 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
498 * We set the maximum voltages allowed here because Smart-Reflex is not
499 * enabled in bootloader. Voltage initialization in the kernel will set
500 * these to the nominal values after enabling Smart-Reflex
502 void scale_vcores(struct vcores_data const *vcores)
504 omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
506 do_scale_vcore(vcores->core.addr, vcores->core.value,
509 do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
512 do_scale_vcore(vcores->mm.addr, vcores->mm.value,
515 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
516 /* Configure LDO SRAM "magic" bits */
517 writel(2, (*prcm)->prm_sldo_core_setup);
518 writel(2, (*prcm)->prm_sldo_mpu_setup);
519 writel(2, (*prcm)->prm_sldo_mm_setup);
523 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
525 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
526 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
527 debug("Enable clock domain - %x\n", clkctrl_reg);
530 static inline void wait_for_clk_enable(u32 clkctrl_addr)
532 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
535 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
536 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
538 clkctrl = readl(clkctrl_addr);
539 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
540 MODULE_CLKCTRL_IDLEST_SHIFT;
542 printf("Clock enable failed for 0x%x idlest 0x%x\n",
543 clkctrl_addr, clkctrl);
549 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
552 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
553 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
554 debug("Enable clock module - %x\n", clkctrl_addr);
556 wait_for_clk_enable(clkctrl_addr);
559 void freq_update_core(void)
561 u32 freq_config1 = 0;
562 const struct dpll_params *core_dpll_params;
563 u32 omap_rev = omap_revision();
565 core_dpll_params = get_core_dpll_params(*dplls_data);
566 /* Put EMIF clock domain in sw wakeup mode */
567 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
568 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
569 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
570 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
572 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
573 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
575 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
576 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
578 freq_config1 |= (core_dpll_params->m2 <<
579 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
580 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
582 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
583 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
584 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
585 puts("FREQ UPDATE procedure failed!!");
590 * Putting EMIF in HW_AUTO is seen to be causing issues with
591 * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
592 * in OMAP5430 ES1.0 silicon
594 if (omap_rev != OMAP5430_ES1_0) {
595 /* Put EMIF clock domain back in hw auto mode */
596 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
597 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
598 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
599 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
603 void bypass_dpll(u32 const base)
605 do_bypass_dpll(base);
606 wait_for_bypass(base);
609 void lock_dpll(u32 const base)
615 void setup_clocks_for_console(void)
617 /* Do not add any spl_debug prints in this function */
618 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
619 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
620 CD_CLKCTRL_CLKTRCTRL_SHIFT);
622 /* Enable all UARTs - console will be on one of them */
623 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
624 MODULE_CLKCTRL_MODULEMODE_MASK,
625 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
626 MODULE_CLKCTRL_MODULEMODE_SHIFT);
628 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
629 MODULE_CLKCTRL_MODULEMODE_MASK,
630 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
631 MODULE_CLKCTRL_MODULEMODE_SHIFT);
633 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
634 MODULE_CLKCTRL_MODULEMODE_MASK,
635 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
636 MODULE_CLKCTRL_MODULEMODE_SHIFT);
638 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
639 MODULE_CLKCTRL_MODULEMODE_MASK,
640 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
641 MODULE_CLKCTRL_MODULEMODE_SHIFT);
643 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
644 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
645 CD_CLKCTRL_CLKTRCTRL_SHIFT);
648 void do_enable_clocks(u32 const *clk_domains,
649 u32 const *clk_modules_hw_auto,
650 u32 const *clk_modules_explicit_en,
655 /* Put the clock domains in SW_WKUP mode */
656 for (i = 0; (i < max) && clk_domains[i]; i++) {
657 enable_clock_domain(clk_domains[i],
658 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
661 /* Clock modules that need to be put in HW_AUTO */
662 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
663 enable_clock_module(clk_modules_hw_auto[i],
664 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
668 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
669 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
670 enable_clock_module(clk_modules_explicit_en[i],
671 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
675 /* Put the clock domains in HW_AUTO mode now */
676 for (i = 0; (i < max) && clk_domains[i]; i++) {
677 enable_clock_domain(clk_domains[i],
678 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
684 switch (omap_hw_init_context()) {
685 case OMAP_INIT_CONTEXT_SPL:
686 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
687 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
688 enable_basic_clocks();
689 scale_vcores(*omap_vcores);
691 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
692 setup_non_essential_dplls();
693 enable_non_essential_clocks();
700 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
701 enable_basic_uboot_clocks();