3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
41 #ifndef CONFIG_SPL_BUILD
43 * printing to console doesn't work unless
44 * this code is executed from SPL
46 #define printf(fmt, args...)
50 static inline u32 __get_sys_clk_index(void)
54 * For ES1 the ROM code calibration of sys clock is not reliable
55 * due to hw issue. So, use hard-coded value. If this value is not
56 * correct for any board over-ride this function in board file
57 * From ES2.0 onwards you will get this information from
60 if (omap_revision() == OMAP4430_ES1_0)
61 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
63 /* SYS_CLKSEL - 1 to match the dpll param array indices */
64 ind = (readl(&prcm->cm_sys_clksel) &
65 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
70 u32 get_sys_clk_index(void)
71 __attribute__ ((weak, alias("__get_sys_clk_index")));
73 u32 get_sys_clk_freq(void)
75 u8 index = get_sys_clk_index();
76 return sys_clk_array[index];
79 static inline void do_bypass_dpll(u32 *const base)
81 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
83 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
84 CM_CLKMODE_DPLL_DPLL_EN_MASK,
85 DPLL_EN_FAST_RELOCK_BYPASS <<
86 CM_CLKMODE_DPLL_EN_SHIFT);
89 static inline void wait_for_bypass(u32 *const base)
91 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
93 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
95 printf("Bypassing DPLL failed %p\n", base);
99 static inline void do_lock_dpll(u32 *const base)
101 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
103 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
104 CM_CLKMODE_DPLL_DPLL_EN_MASK,
105 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
108 static inline void wait_for_lock(u32 *const base)
110 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
112 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
113 &dpll_regs->cm_idlest_dpll, LDELAY)) {
114 printf("DPLL locking failed for %p\n", base);
119 inline u32 check_for_lock(u32 *const base)
121 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
122 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
127 static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
131 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
133 temp = readl(&dpll_regs->cm_clksel_dpll);
135 if (check_for_lock(base)) {
137 * The Dpll has already been locked by rom code using CH.
138 * Check if M,N are matching with Ideal nominal opp values.
139 * If matches, skip the rest otherwise relock.
141 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
142 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
143 if ((M != (params->m)) || (N != (params->n))) {
144 debug("\n %s Dpll locked, but not for ideal M = %d,"
145 "N = %d values, current values are M = %d,"
146 "N= %d" , dpll, params->m, params->n,
149 /* Dpll locked with ideal values for nominal opps. */
150 debug("\n %s Dpll already locked with ideal"
151 "nominal opp values", dpll);
152 goto setup_post_dividers;
159 temp &= ~CM_CLKSEL_DPLL_M_MASK;
160 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
162 temp &= ~CM_CLKSEL_DPLL_N_MASK;
163 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
165 writel(temp, &dpll_regs->cm_clksel_dpll);
172 setup_post_dividers(base, params);
174 /* Wait till the DPLL locks */
179 u32 omap_ddr_clk(void)
181 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
182 const struct dpll_params *core_dpll_params;
184 omap_rev = omap_revision();
185 sys_clk_khz = get_sys_clk_freq() / 1000;
187 core_dpll_params = get_core_dpll_params();
189 debug("sys_clk %d\n ", sys_clk_khz * 1000);
191 /* Find Core DPLL locked frequency first */
192 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
193 (core_dpll_params->n + 1);
195 if (omap_rev < OMAP5430_ES1_0) {
197 * DDR frequency is PHY_ROOT_CLK/2
198 * PHY_ROOT_CLK = Fdpll/2/M2
203 * DDR frequency is PHY_ROOT_CLK
204 * PHY_ROOT_CLK = Fdpll/2/M2
209 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
210 ddr_clk *= 1000; /* convert to Hz */
211 debug("ddr_clk %d\n ", ddr_clk);
219 * Resulting MPU frequencies:
220 * 4430 ES1.0 : 600 MHz
221 * 4430 ES2.x : 792 MHz (OPP Turbo)
222 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
224 void configure_mpu_dpll(void)
226 const struct dpll_params *params;
227 struct dpll_regs *mpu_dpll_regs;
229 omap_rev = omap_revision();
232 * DCC and clock divider settings for 4460.
233 * DCC is required, if more than a certain frequency is required.
237 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
239 (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
240 bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
241 clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
242 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
243 setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
244 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
245 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
246 CM_CLKSEL_DCC_EN_MASK);
249 setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
250 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
251 setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
252 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
254 params = get_mpu_dpll_params();
256 do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
257 debug("MPU DPLL locked\n");
260 #ifdef CONFIG_USB_EHCI_OMAP
261 static void setup_usb_dpll(void)
263 const struct dpll_params *params;
264 u32 sys_clk_khz, sd_div, num, den;
266 sys_clk_khz = get_sys_clk_freq() / 1000;
269 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
270 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
271 * - where CLKINP is sys_clk in MHz
272 * Use CLKINP in KHz and adjust the denominator accordingly so
273 * that we have enough accuracy and at the same time no overflow
275 params = get_usb_dpll_params();
276 num = params->m * sys_clk_khz;
277 den = (params->n + 1) * 250 * 1000;
280 clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
281 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
282 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
284 /* Now setup the dpll with the regular function */
285 do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
289 static void setup_dplls(void)
292 const struct dpll_params *params;
294 debug("setup_dplls\n");
297 params = get_core_dpll_params(); /* default - safest */
299 * Do not lock the core DPLL now. Just set it up.
300 * Core DPLL will be locked after setting up EMIF
301 * using the FREQ_UPDATE method(freq_update_core())
303 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
304 do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
305 DPLL_NO_LOCK, "core");
307 do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
309 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
310 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
311 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
312 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
313 writel(temp, &prcm->cm_clksel_core);
314 debug("Core DPLL configured\n");
317 params = get_per_dpll_params();
318 do_setup_dpll(&prcm->cm_clkmode_dpll_per,
319 params, DPLL_LOCK, "per");
320 debug("PER DPLL locked\n");
323 configure_mpu_dpll();
325 #ifdef CONFIG_USB_EHCI_OMAP
330 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
331 static void setup_non_essential_dplls(void)
334 const struct dpll_params *params;
337 clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
338 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
340 params = get_iva_dpll_params();
341 do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
343 /* Configure ABE dpll */
344 params = get_abe_dpll_params();
345 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
346 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
348 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
350 * We need to enable some additional options to achieve
351 * 196.608MHz from 32768 Hz
353 setbits_le32(&prcm->cm_clkmode_dpll_abe,
354 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
355 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
356 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
357 CM_CLKMODE_DPLL_REGM4XEN_MASK);
358 /* Spend 4 REFCLK cycles at each stage */
359 clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
360 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
361 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
364 /* Select the right reference clk */
365 clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
366 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
367 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
369 do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
373 void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
378 /* See if we can first get the GPIO if needed */
380 ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
382 printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
386 /* Pull the GPIO low to select SET0 register, while we program SET1 */
388 gpio_direction_output(gpio, 0);
390 step = volt_mv - TPS62361_BASE_VOLT_MV;
393 debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
394 if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
395 puts("Scaling voltage failed for vdd_mpu from TPS\n");
397 /* Pull the GPIO high to select SET1 register */
399 gpio_direction_output(gpio, 1);
402 void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
405 u32 offset = volt_mv;
407 /* convert to uV for better accuracy in the calculations */
410 offset_code = get_offset_code(offset);
412 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
415 if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
416 vcore_reg, offset_code))
417 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
420 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
422 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
423 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
424 debug("Enable clock domain - %p\n", clkctrl_reg);
427 static inline void wait_for_clk_enable(u32 *clkctrl_addr)
429 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
432 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
433 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
435 clkctrl = readl(clkctrl_addr);
436 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
437 MODULE_CLKCTRL_IDLEST_SHIFT;
439 printf("Clock enable failed for 0x%p idlest 0x%x\n",
440 clkctrl_addr, clkctrl);
446 static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
449 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
450 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
451 debug("Enable clock module - %p\n", clkctrl_addr);
453 wait_for_clk_enable(clkctrl_addr);
456 void freq_update_core(void)
458 u32 freq_config1 = 0;
459 const struct dpll_params *core_dpll_params;
460 u32 omap_rev = omap_revision();
462 core_dpll_params = get_core_dpll_params();
463 /* Put EMIF clock domain in sw wakeup mode */
464 enable_clock_domain(&prcm->cm_memif_clkstctrl,
465 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
466 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
467 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
469 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
470 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
472 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
473 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
475 freq_config1 |= (core_dpll_params->m2 <<
476 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
477 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
479 writel(freq_config1, &prcm->cm_shadow_freq_config1);
480 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
481 &prcm->cm_shadow_freq_config1, LDELAY)) {
482 puts("FREQ UPDATE procedure failed!!");
487 * Putting EMIF in HW_AUTO is seen to be causing issues with
488 * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
489 * in OMAP5430 ES1.0 silicon
491 if (omap_rev != OMAP5430_ES1_0) {
492 /* Put EMIF clock domain back in hw auto mode */
493 enable_clock_domain(&prcm->cm_memif_clkstctrl,
494 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
495 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
496 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
500 void bypass_dpll(u32 *const base)
502 do_bypass_dpll(base);
503 wait_for_bypass(base);
506 void lock_dpll(u32 *const base)
512 void setup_clocks_for_console(void)
514 /* Do not add any spl_debug prints in this function */
515 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
516 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
517 CD_CLKCTRL_CLKTRCTRL_SHIFT);
519 /* Enable all UARTs - console will be on one of them */
520 clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
521 MODULE_CLKCTRL_MODULEMODE_MASK,
522 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
523 MODULE_CLKCTRL_MODULEMODE_SHIFT);
525 clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
526 MODULE_CLKCTRL_MODULEMODE_MASK,
527 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
528 MODULE_CLKCTRL_MODULEMODE_SHIFT);
530 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
531 MODULE_CLKCTRL_MODULEMODE_MASK,
532 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
533 MODULE_CLKCTRL_MODULEMODE_SHIFT);
535 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
536 MODULE_CLKCTRL_MODULEMODE_MASK,
537 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
538 MODULE_CLKCTRL_MODULEMODE_SHIFT);
540 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
541 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
542 CD_CLKCTRL_CLKTRCTRL_SHIFT);
545 void do_enable_clocks(u32 *const *clk_domains,
546 u32 *const *clk_modules_hw_auto,
547 u32 *const *clk_modules_explicit_en,
552 /* Put the clock domains in SW_WKUP mode */
553 for (i = 0; (i < max) && clk_domains[i]; i++) {
554 enable_clock_domain(clk_domains[i],
555 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
558 /* Clock modules that need to be put in HW_AUTO */
559 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
560 enable_clock_module(clk_modules_hw_auto[i],
561 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
565 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
566 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
567 enable_clock_module(clk_modules_explicit_en[i],
568 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
572 /* Put the clock domains in HW_AUTO mode now */
573 for (i = 0; (i < max) && clk_domains[i]; i++) {
574 enable_clock_domain(clk_domains[i],
575 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
581 switch (omap_hw_init_context()) {
582 case OMAP_INIT_CONTEXT_SPL:
583 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
584 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
585 enable_basic_clocks();
588 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
589 setup_non_essential_dplls();
590 enable_non_essential_clocks();
597 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
598 enable_basic_uboot_clocks();