1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
5 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
9 #include <linux/linkage.h>
11 #include <asm/armv7.h>
12 #include <asm/proc-armv/ptrace.h>
17 .pushsection ._secure.text, "ax"
20 /* the vector table for secure state and HYP mode */
24 adr pc, _secure_monitor
31 .macro is_cpu_virt_capable tmp
32 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
33 and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
34 cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
38 * secure monitor handler
39 * U-Boot calls this "software interrupt" in start.S
40 * This is executed on a "smc" instruction, we use a "smc #0" to switch
41 * to non-secure state.
42 * r0, r1, r2: passed to the callee
46 #ifdef CONFIG_ARMV7_PSCI
47 ldr r5, =_psci_vectors @ Switch to the next monitor
48 mcr p15, 0, r5, c12, c0, 1
51 @ Obtain a secure stack
54 @ Configure the PSCI backend
60 #ifdef CONFIG_ARM_ERRATA_773022
61 mrc p15, 0, r5, c1, c0, 1
63 mcr p15, 0, r5, c1, c0, 1
67 #ifdef CONFIG_ARM_ERRATA_774769
68 mrc p15, 0, r5, c1, c0, 1
69 orr r5, r5, #(1 << 25)
70 mcr p15, 0, r5, c1, c0, 1
74 mrc p15, 0, r5, c1, c1, 0 @ read SCR
75 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
76 orr r5, r5, #0x31 @ enable NS, AW, FW bits
77 @ FIQ preserved for secure mode
78 mov r6, #SVC_MODE @ default mode is SVC
79 is_cpu_virt_capable r4
80 #ifdef CONFIG_ARMV7_VIRT
81 orreq r5, r5, #0x100 @ allow HVC instruction
82 moveq r6, #HYP_MODE @ Enter the kernel as HYP
84 msreq sp_hyp, r3 @ migrate SP
87 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
92 @ Reset CNTVOFF to 0 before leaving monitor mode
93 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
94 ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
96 mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
99 mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
100 tst lr, #1 @ Check for Thumb PC
101 orrne ip, ip, #T_BIT @ Set T if Thumb
102 orr ip, ip, r6 @ Slot target mode in
103 msr spsr_cxfs, ip @ Set full SPSR
104 movs pc, lr @ ERET to non-secure
106 ENTRY(_do_nonsec_entry)
112 ENDPROC(_do_nonsec_entry)
114 .macro get_cbar_addr addr
115 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
116 ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
118 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
119 bfc \addr, #0, #15 @ clear reserved bits
123 .macro get_gicd_addr addr
125 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
128 .macro get_gicc_addr addr, tmp
130 is_cpu_virt_capable \tmp
131 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
132 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
133 add \addr, \addr, \tmp
136 #ifndef CONFIG_ARMV7_PSCI
138 * Secondary CPUs start here and call the code for the core specific parts
139 * of the non-secure and HYP mode transition. The GIC distributor specific
140 * code has already been executed by a C function before.
141 * Then they go back to wfi and wait to be woken up by the kernel again.
149 adr r0, _smp_pen @ do not use this address again
150 b smp_waitloop @ wait for IPIs, board specific
155 * Switch a core to non-secure state.
157 * 1. initialize the GIC per-core interface
158 * 2. allow coprocessor access in non-secure modes
160 * Called from smp_pen by secondary cores and directly by the BSP.
161 * Do not assume that the stack is available and only use registers
164 * PERIPHBASE is used to get the GIC address. This could be 40 bits long,
165 * though, but we check this in C before calling this function.
170 mvn r1, #0 @ all bits to 1
171 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
175 mov r1, #3 @ Enable both groups
176 str r1, [r3, #GICC_CTLR] @ and clear all other bits
178 str r1, [r3, #GICC_PMR] @ set priority mask register
180 mrc p15, 0, r0, c1, c1, 2
184 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
186 /* The CNTFRQ register of the generic timer needs to be
187 * programmed in secure state. Some primary bootloaders / firmware
188 * omit this, so if the frequency is provided in the configuration,
189 * we do this here instead.
190 * But first check if we have the generic timer.
192 #ifdef COUNTER_FREQUENCY
193 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
194 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
195 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
196 ldreq r1, =COUNTER_FREQUENCY
197 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
200 adr r1, _monitor_vectors
201 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
204 mov r0, r3 @ return GICC address
206 ENDPROC(_nonsec_init)
208 #ifdef CONFIG_SMP_PEN_ADDR
209 /* void __weak smp_waitloop(unsigned previous_address); */
212 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
214 #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
217 cmp r0, r1 @ make sure we dont execute this code
218 beq smp_waitloop @ again (due to a spurious wakeup)
221 ENDPROC(smp_waitloop)