arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_SYS,        /* System PLL */
  18         PLL_BUS,        /* System Bus PLL*/
  19         PLL_USBOTG,     /* OTG USB PLL */
  20         PLL_ENET,       /* ENET PLL */
  21 };
  22
  23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  24
  25 #ifdef CONFIG_MXC_OCOTP
  26 void enable_ocotp_clk(unsigned char enable)
  27 {
  28         u32 reg;
  29
  30         reg = __raw_readl(&imx_ccm->CCGR2);
  31         if (enable)
  32                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  33         else
  34                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  35         __raw_writel(reg, &imx_ccm->CCGR2);
  36 }
  37 #endif
  38
  39 #ifdef CONFIG_NAND_MXS
  40 void setup_gpmi_io_clk(u32 cfg)
  41 {
  42         /* Disable clocks per ERR007177 from MX6 errata */
  43         clrbits_le32(&imx_ccm->CCGR4,
  44                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  45                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  46                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  47                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  48                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  49
  50         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  51
  52         clrsetbits_le32(&imx_ccm->cs2cdr,
  53                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  54                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  55                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  56                         cfg);
  57
  58         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  59         setbits_le32(&imx_ccm->CCGR4,
  60                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  61                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  62                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  63                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  64                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  65 }
  66 #endif
  67
  68 void enable_usboh3_clk(unsigned char enable)
  69 {
  70         u32 reg;
  71
  72         reg = __raw_readl(&imx_ccm->CCGR6);
  73         if (enable)
  74                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  75         else
  76                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  77         __raw_writel(reg, &imx_ccm->CCGR6);
  78
  79 }
  80
  81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  82 void enable_enet_clk(unsigned char enable)
  83 {
  84         u32 mask, *addr;
  85
  86         if (is_cpu_type(MXC_CPU_MX6UL)) {
  87                 mask = MXC_CCM_CCGR3_ENET_MASK;
  88                 addr = &imx_ccm->CCGR3;
  89         } else {
  90                 mask = MXC_CCM_CCGR1_ENET_MASK;
  91                 addr = &imx_ccm->CCGR1;
  92         }
  93
  94         if (enable)
  95                 setbits_le32(addr, mask);
  96         else
  97                 clrbits_le32(addr, mask);
  98 }
  99 #endif
 100
 101 #ifdef CONFIG_MXC_UART
 102 void enable_uart_clk(unsigned char enable)
 103 {
 104         u32 mask;
 105
 106         if (is_cpu_type(MXC_CPU_MX6UL))
 107                 mask = MXC_CCM_CCGR5_UART_MASK;
 108         else
 109                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 110
 111         if (enable)
 112                 setbits_le32(&imx_ccm->CCGR5, mask);
 113         else
 114                 clrbits_le32(&imx_ccm->CCGR5, mask);
 115 }
 116 #endif
 117
 118 #ifdef CONFIG_MMC
 119 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 120 {
 121         u32 mask;
 122
 123         if (bus_num > 3)
 124                 return -EINVAL;
 125
 126         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 127         if (enable)
 128                 setbits_le32(&imx_ccm->CCGR6, mask);
 129         else
 130                 clrbits_le32(&imx_ccm->CCGR6, mask);
 131
 132         return 0;
 133 }
 134 #endif
 135
 136 #ifdef CONFIG_SYS_I2C_MXC
 137 /* i2c_num can be from 0 - 3 */
 138 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 139 {
 140         u32 reg;
 141         u32 mask;
 142         u32 *addr;
 143
 144         if (i2c_num > 3)
 145                 return -EINVAL;
 146         if (i2c_num < 3) {
 147                 mask = MXC_CCM_CCGR_CG_MASK
 148                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 149                         + (i2c_num << 1));
 150                 reg = __raw_readl(&imx_ccm->CCGR2);
 151                 if (enable)
 152                         reg |= mask;
 153                 else
 154                         reg &= ~mask;
 155                 __raw_writel(reg, &imx_ccm->CCGR2);
 156         } else {
 157                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 158                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 159                         addr = &imx_ccm->CCGR6;
 160                 } else {
 161                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 162                         addr = &imx_ccm->CCGR1;
 163                 }
 164                 reg = __raw_readl(addr);
 165                 if (enable)
 166                         reg |= mask;
 167                 else
 168                         reg &= ~mask;
 169                 __raw_writel(reg, addr);
 170         }
 171         return 0;
 172 }
 173 #endif
 174
 175 /* spi_num can be from 0 - SPI_MAX_NUM */
 176 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 177 {
 178         u32 reg;
 179         u32 mask;
 180
 181         if (spi_num > SPI_MAX_NUM)
 182                 return -EINVAL;
 183
 184         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 185         reg = __raw_readl(&imx_ccm->CCGR1);
 186         if (enable)
 187                 reg |= mask;
 188         else
 189                 reg &= ~mask;
 190         __raw_writel(reg, &imx_ccm->CCGR1);
 191         return 0;
 192 }
 193 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 194 {
 195         u32 div;
 196
 197         switch (pll) {
 198         case PLL_SYS:
 199                 div = __raw_readl(&imx_ccm->analog_pll_sys);
 200                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 201
 202                 return (infreq * div) >> 1;
 203         case PLL_BUS:
 204                 div = __raw_readl(&imx_ccm->analog_pll_528);
 205                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 206
 207                 return infreq * (20 + (div << 1));
 208         case PLL_USBOTG:
 209                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
 210                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 211
 212                 return infreq * (20 + (div << 1));
 213         case PLL_ENET:
 214                 div = __raw_readl(&imx_ccm->analog_pll_enet);
 215                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 216
 217                 return 25000000 * (div + (div >> 1) + 1);
 218         default:
 219                 return 0;
 220         }
 221         /* NOTREACHED */
 222 }
 223 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 224 {
 225         u32 div;
 226         u64 freq;
 227
 228         switch (pll) {
 229         case PLL_BUS:
 230                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 231                         if (pfd_num == 3) {
 232                                 /* No PFD3 on PPL2 */
 233                                 return 0;
 234                         }
 235                 }
 236                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 237                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 238                 break;
 239         case PLL_USBOTG:
 240                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 241                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 242                 break;
 243         default:
 244                 /* No PFD on other PLL                                       */
 245                 return 0;
 246         }
 247
 248         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 249                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 250 }
 251
 252 static u32 get_mcu_main_clk(void)
 253 {
 254         u32 reg, freq;
 255
 256         reg = __raw_readl(&imx_ccm->cacrr);
 257         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 258         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 259         freq = decode_pll(PLL_SYS, MXC_HCLK);
 260
 261         return freq / (reg + 1);
 262 }
 263
 264 u32 get_periph_clk(void)
 265 {
 266         u32 reg, div = 0, freq = 0;
 267
 268         reg = __raw_readl(&imx_ccm->cbcdr);
 269         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 270                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 271                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 272                 reg = __raw_readl(&imx_ccm->cbcmr);
 273                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 274                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 275
 276                 switch (reg) {
 277                 case 0:
 278                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 279                         break;
 280                 case 1:
 281                 case 2:
 282                         freq = MXC_HCLK;
 283                         break;
 284                 default:
 285                         break;
 286                 }
 287         } else {
 288                 reg = __raw_readl(&imx_ccm->cbcmr);
 289                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 290                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 291
 292                 switch (reg) {
 293                 case 0:
 294                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 295                         break;
 296                 case 1:
 297                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 298                         break;
 299                 case 2:
 300                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 301                         break;
 302                 case 3:
 303                         /* static / 2 divider */
 304                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 305                         break;
 306                 default:
 307                         break;
 308                 }
 309         }
 310
 311         return freq / (div + 1);
 312 }
 313
 314 static u32 get_ipg_clk(void)
 315 {
 316         u32 reg, ipg_podf;
 317
 318         reg = __raw_readl(&imx_ccm->cbcdr);
 319         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 320         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 321
 322         return get_ahb_clk() / (ipg_podf + 1);
 323 }
 324
 325 static u32 get_ipg_per_clk(void)
 326 {
 327         u32 reg, perclk_podf;
 328
 329         reg = __raw_readl(&imx_ccm->cscmr1);
 330         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 331             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 332                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 333                         return MXC_HCLK; /* OSC 24Mhz */
 334         }
 335
 336         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 337
 338         return get_ipg_clk() / (perclk_podf + 1);
 339 }
 340
 341 static u32 get_uart_clk(void)
 342 {
 343         u32 reg, uart_podf;
 344         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 345         reg = __raw_readl(&imx_ccm->cscdr1);
 346
 347         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 348             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 349                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 350                         freq = MXC_HCLK;
 351         }
 352
 353         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 354         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 355
 356         return freq / (uart_podf + 1);
 357 }
 358
 359 static u32 get_cspi_clk(void)
 360 {
 361         u32 reg, cspi_podf;
 362
 363         reg = __raw_readl(&imx_ccm->cscdr2);
 364         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 365                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 366
 367         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 368             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 369                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 370                         return MXC_HCLK / (cspi_podf + 1);
 371         }
 372
 373         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 374 }
 375
 376 static u32 get_axi_clk(void)
 377 {
 378         u32 root_freq, axi_podf;
 379         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 380
 381         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 382         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 383
 384         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 385                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 386                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 387                 else
 388                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 389         } else
 390                 root_freq = get_periph_clk();
 391
 392         return  root_freq / (axi_podf + 1);
 393 }
 394
 395 static u32 get_emi_slow_clk(void)
 396 {
 397         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 398
 399         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 400         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 401         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 402         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 403         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 404
 405         switch (emi_clk_sel) {
 406         case 0:
 407                 root_freq = get_axi_clk();
 408                 break;
 409         case 1:
 410                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 411                 break;
 412         case 2:
 413                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 414                 break;
 415         case 3:
 416                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 417                 break;
 418         }
 419
 420         return root_freq / (emi_slow_podf + 1);
 421 }
 422
 423 static u32 get_mmdc_ch0_clk(void)
 424 {
 425         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 426         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 427
 428         u32 freq, podf, per2_clk2_podf;
 429
 430         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 431             is_cpu_type(MXC_CPU_MX6SL)) {
 432                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 433                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 434                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 435                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 436                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 437                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 438                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 439                                         freq = MXC_HCLK;
 440                                 else
 441                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 442                         } else {
 443                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 444                                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 445                                 else
 446                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 447                         }
 448                 } else {
 449                         per2_clk2_podf = 0;
 450                         switch ((cbcmr &
 451                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 452                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 453                         case 0:
 454                                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 455                                 break;
 456                         case 1:
 457                                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 458                                 break;
 459                         case 2:
 460                                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 461                                 break;
 462                         case 3:
 463                                 /* static / 2 divider */
 464                                 freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 465                                 break;
 466                         }
 467                 }
 468                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 469         } else {
 470                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 471                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 472                 return get_periph_clk() / (podf + 1);
 473         }
 474 }
 475
 476 #if defined(CONFIG_VIDEO_MXS)
 477 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
 478                             u32 post_div)
 479 {
 480         u32 reg = 0;
 481         ulong start;
 482
 483         debug("pll5 div = %d, num = %d, denom = %d\n",
 484               pll_div, pll_num, pll_denom);
 485
 486         /* Power up PLL5 video */
 487         writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
 488                BM_ANADIG_PLL_VIDEO_BYPASS |
 489                BM_ANADIG_PLL_VIDEO_DIV_SELECT |
 490                BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
 491                &imx_ccm->analog_pll_video_clr);
 492
 493         /* Set div, num and denom */
 494         switch (post_div) {
 495         case 1:
 496                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 497                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
 498                        &imx_ccm->analog_pll_video_set);
 499                 break;
 500         case 2:
 501                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 502                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
 503                        &imx_ccm->analog_pll_video_set);
 504                 break;
 505         case 4:
 506                 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
 507                        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
 508                        &imx_ccm->analog_pll_video_set);
 509                 break;
 510         default:
 511                 puts("Wrong test_div!\n");
 512                 return -EINVAL;
 513         }
 514
 515         writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
 516                &imx_ccm->analog_pll_video_num);
 517         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
 518                &imx_ccm->analog_pll_video_denom);
 519
 520         /* Wait PLL5 lock */
 521         start = get_timer(0);   /* Get current timestamp */
 522
 523         do {
 524                 reg = readl(&imx_ccm->analog_pll_video);
 525                 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
 526                         /* Enable PLL out */
 527                         writel(BM_ANADIG_PLL_VIDEO_ENABLE,
 528                                &imx_ccm->analog_pll_video_set);
 529                         return 0;
 530                 }
 531         } while (get_timer(0) < (start + 10)); /* Wait 10ms */
 532
 533         puts("Lock PLL5 timeout\n");
 534
 535         return -ETIME;
 536 }
 537
 538 /*
 539  * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
 540  *
 541  * 'freq' using KHz as unit, see driver/video/mxsfb.c.
 542  */
 543 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 544 {
 545         u32 reg = 0;
 546         u32 hck = MXC_HCLK / 1000;
 547         /* DIV_SELECT ranges from 27 to 54 */
 548         u32 min = hck * 27;
 549         u32 max = hck * 54;
 550         u32 temp, best = 0;
 551         u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
 552         u32 pll_div, pll_num, pll_denom, post_div = 1;
 553
 554         debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 555
 556         if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
 557                 debug("This chip not support lcd!\n");
 558                 return;
 559         }
 560
 561         if (base_addr == LCDIF1_BASE_ADDR) {
 562                 reg = readl(&imx_ccm->cscdr2);
 563                 /* Can't change clocks when clock not from pre-mux */
 564                 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
 565                         return;
 566         }
 567
 568         if (is_cpu_type(MXC_CPU_MX6SX)) {
 569                 reg = readl(&imx_ccm->cscdr2);
 570                 /* Can't change clocks when clock not from pre-mux */
 571                 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
 572                         return;
 573         }
 574
 575         temp = freq * max_pred * max_postd;
 576         if (temp > max) {
 577                 puts("Please decrease freq, too large!\n");
 578                 return;
 579         }
 580         if (temp < min) {
 581                 /*
 582                  * Register: PLL_VIDEO
 583                  * Bit Field: POST_DIV_SELECT
 584                  * 00 — Divide by 4.
 585                  * 01 — Divide by 2.
 586                  * 10 — Divide by 1.
 587                  * 11 — Reserved
 588                  * No need to check post_div(1)
 589                  */
 590                 for (post_div = 2; post_div <= 4; post_div <<= 1) {
 591                         if ((temp * post_div) > min) {
 592                                 freq *= post_div;
 593                                 break;
 594                         }
 595                 }
 596
 597                 if (post_div > 4) {
 598                         printf("Fail to set rate to %dkhz", freq);
 599                         return;
 600                 }
 601         }
 602
 603         /* Choose the best pred and postd to match freq for lcd */
 604         for (i = 1; i <= max_pred; i++) {
 605                 for (j = 1; j <= max_postd; j++) {
 606                         temp = freq * i * j;
 607                         if (temp > max || temp < min)
 608                                 continue;
 609                         if (best == 0 || temp < best) {
 610                                 best = temp;
 611                                 pred = i;
 612                                 postd = j;
 613                         }
 614                 }
 615         }
 616
 617         if (best == 0) {
 618                 printf("Fail to set rate to %dKHz", freq);
 619                 return;
 620         }
 621
 622         debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
 623
 624         pll_div = best / hck;
 625         pll_denom = 1000000;
 626         pll_num = (best - hck * pll_div) * pll_denom / hck;
 627
 628         /*
 629          *                                  pll_num
 630          *             (24MHz * (pll_div + --------- ))
 631          *                                 pll_denom
 632          *freq KHz =  --------------------------------
 633          *             post_div * pred * postd * 1000
 634          */
 635
 636         if (base_addr == LCDIF1_BASE_ADDR) {
 637                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 638                         return;
 639
 640                 /* Select pre-lcd clock to PLL5 and set pre divider */
 641                 clrsetbits_le32(&imx_ccm->cscdr2,
 642                                 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
 643                                 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
 644                                 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
 645                                 ((pred - 1) <<
 646                                  MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
 647
 648                 /* Set the post divider */
 649                 clrsetbits_le32(&imx_ccm->cbcmr,
 650                                 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
 651                                 ((postd - 1) <<
 652                                  MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
 653         } else if (is_cpu_type(MXC_CPU_MX6SX)) {
 654                 /* Setting LCDIF2 for i.MX6SX */
 655                 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 656                         return;
 657
 658                 /* Select pre-lcd clock to PLL5 and set pre divider */
 659                 clrsetbits_le32(&imx_ccm->cscdr2,
 660                                 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
 661                                 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
 662                                 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
 663                                 ((pred - 1) <<
 664                                  MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
 665
 666                 /* Set the post divider */
 667                 clrsetbits_le32(&imx_ccm->cscmr1,
 668                                 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
 669                                 ((postd - 1) <<
 670                                  MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 671         }
 672 }
 673
 674 int enable_lcdif_clock(u32 base_addr)
 675 {
 676         u32 reg = 0;
 677         u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 678
 679         if (is_cpu_type(MXC_CPU_MX6SX)) {
 680                 if ((base_addr == LCDIF1_BASE_ADDR) ||
 681                     (base_addr == LCDIF2_BASE_ADDR)) {
 682                         puts("Wrong LCD interface!\n");
 683                         return -EINVAL;
 684                 }
 685                 /* Set to pre-mux clock at default */
 686                 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 687                         MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
 688                         MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 689                 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
 690                         (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
 691                          MXC_CCM_CCGR3_DISP_AXI_MASK) :
 692                         (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 693                          MXC_CCM_CCGR3_DISP_AXI_MASK);
 694         } else if (is_cpu_type(MXC_CPU_MX6UL)) {
 695                 if (base_addr != LCDIF1_BASE_ADDR) {
 696                         puts("Wrong LCD interface!\n");
 697                         return -EINVAL;
 698                 }
 699                 /* Set to pre-mux clock at default */
 700                 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 701                 lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
 702         } else {
 703                 return 0;
 704         }
 705
 706         reg = readl(&imx_ccm->cscdr2);
 707         reg &= ~lcdif_clk_sel_mask;
 708         writel(reg, &imx_ccm->cscdr2);
 709
 710         /* Enable the LCDIF pix clock */
 711         reg = readl(&imx_ccm->CCGR3);
 712         reg |= lcdif_ccgr3_mask;
 713         writel(reg, &imx_ccm->CCGR3);
 714
 715         reg = readl(&imx_ccm->CCGR2);
 716         reg |= MXC_CCM_CCGR2_LCD_MASK;
 717         writel(reg, &imx_ccm->CCGR2);
 718 }
 719 #endif
 720
 721 #ifdef CONFIG_FSL_QSPI
 722 /* qspi_num can be from 0 - 1 */
 723 void enable_qspi_clk(int qspi_num)
 724 {
 725         u32 reg = 0;
 726         /* Enable QuadSPI clock */
 727         switch (qspi_num) {
 728         case 0:
 729                 /* disable the clock gate */
 730                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 731
 732                 /* set 50M  : (50 = 396 / 2 / 4) */
 733                 reg = readl(&imx_ccm->cscmr1);
 734                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 735                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 736                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 737                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 738                 writel(reg, &imx_ccm->cscmr1);
 739
 740                 /* enable the clock gate */
 741                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 742                 break;
 743         case 1:
 744                 /*
 745                  * disable the clock gate
 746                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 747                  * disable both of them.
 748                  */
 749                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 750                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 751
 752                 /* set 50M  : (50 = 396 / 2 / 4) */
 753                 reg = readl(&imx_ccm->cs2cdr);
 754                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 755                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 756                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 757                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 758                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 759                 writel(reg, &imx_ccm->cs2cdr);
 760
 761                 /*enable the clock gate*/
 762                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 763                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 764                 break;
 765         default:
 766                 break;
 767         }
 768 }
 769 #endif
 770
 771 #ifdef CONFIG_FEC_MXC
 772 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 773 {
 774         u32 reg = 0;
 775         s32 timeout = 100000;
 776
 777         struct anatop_regs __iomem *anatop =
 778                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 779
 780         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 781                 return -EINVAL;
 782
 783         reg = readl(&anatop->pll_enet);
 784
 785         if (fec_id == 0) {
 786                 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 787                 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 788         } else if (fec_id == 1) {
 789                 /* Only i.MX6SX/UL support ENET2 */
 790                 if (!(is_cpu_type(MXC_CPU_MX6SX) ||
 791                       is_cpu_type(MXC_CPU_MX6UL)))
 792                         return -EINVAL;
 793                 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 794                 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
 795         } else {
 796                 return -EINVAL;
 797         }
 798
 799         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 800             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 801                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 802                 writel(reg, &anatop->pll_enet);
 803                 while (timeout--) {
 804                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 805                                 break;
 806                 }
 807                 if (timeout < 0)
 808                         return -ETIMEDOUT;
 809         }
 810
 811         /* Enable FEC clock */
 812         if (fec_id == 0)
 813                 reg |= BM_ANADIG_PLL_ENET_ENABLE;
 814         else
 815                 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
 816         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 817         writel(reg, &anatop->pll_enet);
 818
 819 #ifdef CONFIG_MX6SX
 820         /*
 821          * Set enet ahb clock to 200MHz
 822          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 823          */
 824         reg = readl(&imx_ccm->chsccdr);
 825         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 826                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 827                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 828         /* PLL2 PFD2 */
 829         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 830         /* Div = 2*/
 831         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 832         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 833         writel(reg, &imx_ccm->chsccdr);
 834
 835         /* Enable enet system clock */
 836         reg = readl(&imx_ccm->CCGR3);
 837         reg |= MXC_CCM_CCGR3_ENET_MASK;
 838         writel(reg, &imx_ccm->CCGR3);
 839 #endif
 840         return 0;
 841 }
 842 #endif
 843
 844 static u32 get_usdhc_clk(u32 port)
 845 {
 846         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 847         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 848         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 849
 850         switch (port) {
 851         case 0:
 852                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 853                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 854                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 855
 856                 break;
 857         case 1:
 858                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 859                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 860                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 861
 862                 break;
 863         case 2:
 864                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 865                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 866                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 867
 868                 break;
 869         case 3:
 870                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 871                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 872                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 873
 874                 break;
 875         default:
 876                 break;
 877         }
 878
 879         if (clk_sel)
 880                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 881         else
 882                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 883
 884         return root_freq / (usdhc_podf + 1);
 885 }
 886
 887 u32 imx_get_uartclk(void)
 888 {
 889         return get_uart_clk();
 890 }
 891
 892 u32 imx_get_fecclk(void)
 893 {
 894         return mxc_get_clock(MXC_IPG_CLK);
 895 }
 896
 897 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 898 static int enable_enet_pll(uint32_t en)
 899 {
 900         struct mxc_ccm_reg *const imx_ccm
 901                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
 902         s32 timeout = 100000;
 903         u32 reg = 0;
 904
 905         /* Enable PLLs */
 906         reg = readl(&imx_ccm->analog_pll_enet);
 907         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 908         writel(reg, &imx_ccm->analog_pll_enet);
 909         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 910         while (timeout--) {
 911                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 912                         break;
 913         }
 914         if (timeout <= 0)
 915                 return -EIO;
 916         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 917         writel(reg, &imx_ccm->analog_pll_enet);
 918         reg |= en;
 919         writel(reg, &imx_ccm->analog_pll_enet);
 920         return 0;
 921 }
 922 #endif
 923
 924 #ifdef CONFIG_CMD_SATA
 925 static void ungate_sata_clock(void)
 926 {
 927         struct mxc_ccm_reg *const imx_ccm =
 928                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 929
 930         /* Enable SATA clock. */
 931         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 932 }
 933
 934 int enable_sata_clock(void)
 935 {
 936         ungate_sata_clock();
 937         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 938 }
 939
 940 void disable_sata_clock(void)
 941 {
 942         struct mxc_ccm_reg *const imx_ccm =
 943                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 944
 945         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 946 }
 947 #endif
 948
 949 #ifdef CONFIG_PCIE_IMX
 950 static void ungate_pcie_clock(void)
 951 {
 952         struct mxc_ccm_reg *const imx_ccm =
 953                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 954
 955         /* Enable PCIe clock. */
 956         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 957 }
 958
 959 int enable_pcie_clock(void)
 960 {
 961         struct anatop_regs *anatop_regs =
 962                 (struct anatop_regs *)ANATOP_BASE_ADDR;
 963         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 964         u32 lvds1_clk_sel;
 965
 966         /*
 967          * Here be dragons!
 968          *
 969          * The register ANATOP_MISC1 is not documented in the Freescale
 970          * MX6RM. The register that is mapped in the ANATOP space and
 971          * marked as ANATOP_MISC1 is actually documented in the PMU section
 972          * of the datasheet as PMU_MISC1.
 973          *
 974          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 975          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 976          * for PCI express link that is clocked from the i.MX6.
 977          */
 978 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 979 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 980 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 981 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 982 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 983
 984         if (is_cpu_type(MXC_CPU_MX6SX))
 985                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 986         else
 987                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 988
 989         clrsetbits_le32(&anatop_regs->ana_misc1,
 990                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 991                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 992                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 993
 994         /* PCIe reference clock sourced from AXI. */
 995         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 996
 997         /* Party time! Ungate the clock to the PCIe. */
 998 #ifdef CONFIG_CMD_SATA
 999         ungate_sata_clock();
1000 #endif
1001         ungate_pcie_clock();
1002
1003         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1004                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1005 }
1006 #endif
1007
1008 #ifdef CONFIG_SECURE_BOOT
1009 void hab_caam_clock_enable(unsigned char enable)
1010 {
1011         u32 reg;
1012
1013         /* CG4 ~ CG6, CAAM clocks */
1014         reg = __raw_readl(&imx_ccm->CCGR0);
1015         if (enable)
1016                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1017                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1018                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1019         else
1020                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1021                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1022                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1023         __raw_writel(reg, &imx_ccm->CCGR0);
1024
1025         /* EMI slow clk */
1026         reg = __raw_readl(&imx_ccm->CCGR6);
1027         if (enable)
1028                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1029         else
1030                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1031         __raw_writel(reg, &imx_ccm->CCGR6);
1032 }
1033 #endif
1034
1035 static void enable_pll3(void)
1036 {
1037         struct anatop_regs __iomem *anatop =
1038                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1039
1040         /* make sure pll3 is enabled */
1041         if ((readl(&anatop->usb1_pll_480_ctrl) &
1042                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1043                 /* enable pll's power */
1044                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1045                        &anatop->usb1_pll_480_ctrl_set);
1046                 writel(0x80, &anatop->ana_misc2_clr);
1047                 /* wait for pll lock */
1048                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1049                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1050                         ;
1051                 /* disable bypass */
1052                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1053                        &anatop->usb1_pll_480_ctrl_clr);
1054                 /* enable pll output */
1055                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1056                        &anatop->usb1_pll_480_ctrl_set);
1057         }
1058 }
1059
1060 void enable_thermal_clk(void)
1061 {
1062         enable_pll3();
1063 }
1064
1065 unsigned int mxc_get_clock(enum mxc_clock clk)
1066 {
1067         switch (clk) {
1068         case MXC_ARM_CLK:
1069                 return get_mcu_main_clk();
1070         case MXC_PER_CLK:
1071                 return get_periph_clk();
1072         case MXC_AHB_CLK:
1073                 return get_ahb_clk();
1074         case MXC_IPG_CLK:
1075                 return get_ipg_clk();
1076         case MXC_IPG_PERCLK:
1077         case MXC_I2C_CLK:
1078                 return get_ipg_per_clk();
1079         case MXC_UART_CLK:
1080                 return get_uart_clk();
1081         case MXC_CSPI_CLK:
1082                 return get_cspi_clk();
1083         case MXC_AXI_CLK:
1084                 return get_axi_clk();
1085         case MXC_EMI_SLOW_CLK:
1086                 return get_emi_slow_clk();
1087         case MXC_DDR_CLK:
1088                 return get_mmdc_ch0_clk();
1089         case MXC_ESDHC_CLK:
1090                 return get_usdhc_clk(0);
1091         case MXC_ESDHC2_CLK:
1092                 return get_usdhc_clk(1);
1093         case MXC_ESDHC3_CLK:
1094                 return get_usdhc_clk(2);
1095         case MXC_ESDHC4_CLK:
1096                 return get_usdhc_clk(3);
1097         case MXC_SATA_CLK:
1098                 return get_ahb_clk();
1099         default:
1100                 printf("Unsupported MXC CLK: %d\n", clk);
1101                 break;
1102         }
1103
1104         return 0;
1105 }
1106
1107 /*
1108  * Dump some core clockes.
1109  */
1110 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1111 {
1112         u32 freq;
1113         freq = decode_pll(PLL_SYS, MXC_HCLK);
1114         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
1115         freq = decode_pll(PLL_BUS, MXC_HCLK);
1116         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
1117         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1118         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
1119         freq = decode_pll(PLL_ENET, MXC_HCLK);
1120         printf("PLL_NET    %8d MHz\n", freq / 1000000);
1121
1122         printf("\n");
1123         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1124         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1125 #ifdef CONFIG_MXC_SPI
1126         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1127 #endif
1128         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1129         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1130         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1131         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1132         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1133         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1134         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1135         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1136         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1137
1138         return 0;
1139 }
1140
1141 #ifndef CONFIG_MX6SX
1142 void enable_ipu_clock(void)
1143 {
1144         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1145         int reg;
1146         reg = readl(&mxc_ccm->CCGR3);
1147         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1148         writel(reg, &mxc_ccm->CCGR3);
1149
1150         if (is_mx6dqp()) {
1151                 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1152                 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1153         }
1154 }
1155 #endif
1156 /***************************************************/
1157
1158 U_BOOT_CMD(
1159         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1160         "display clocks",
1161         ""
1162 );