3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
43 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
44 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
45 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
46 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
48 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
52 #define AHB_CLK_ROOT 133333333
53 #define SZ_DEC_1M 1000000
54 #define PLL_PD_MAX 16 /* Actual pd+1 */
55 #define PLL_MFI_MAX 15
63 #define MX5_CBCMR 0x00015154
64 #define MX5_CBCDR 0x02888945
66 struct fixed_pll_mfd {
71 const struct fixed_pll_mfd fixed_mfd[] = {
82 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
83 #define PLL_FREQ_MIN(ref_clk) \
84 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
85 #define MAX_DDR_CLK 420000000
86 #define NFC_CLK_MAX 34000000
88 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
90 void set_usboh3_clk(void)
92 clrsetbits_le32(&mxc_ccm->cscmr1,
93 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
94 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
95 clrsetbits_le32(&mxc_ccm->cscdr1,
96 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
97 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
98 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
99 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
102 void enable_usboh3_clk(unsigned char enable)
104 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
106 clrsetbits_le32(&mxc_ccm->CCGR2,
107 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
108 MXC_CCM_CCGR2_USBOH3_60M(cg));
111 #ifdef CONFIG_I2C_MXC
112 /* i2c_num can be from 0 - 2 */
113 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
119 mask = MXC_CCM_CCGR_CG_MASK <<
120 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
122 setbits_le32(&mxc_ccm->CCGR1, mask);
124 clrbits_le32(&mxc_ccm->CCGR1, mask);
129 void set_usb_phy1_clk(void)
131 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
134 void enable_usb_phy1_clk(unsigned char enable)
136 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
138 clrsetbits_le32(&mxc_ccm->CCGR4,
139 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
140 MXC_CCM_CCGR4_USB_PHY1(cg));
143 void set_usb_phy2_clk(void)
145 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
148 void enable_usb_phy2_clk(unsigned char enable)
150 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
152 clrsetbits_le32(&mxc_ccm->CCGR4,
153 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
154 MXC_CCM_CCGR4_USB_PHY2(cg));
158 * Calculate the frequency of PLLn.
160 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
162 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
163 uint64_t refclk, temp;
166 ctrl = readl(&pll->ctrl);
168 if (ctrl & MXC_DPLLC_CTL_HFSM) {
169 mfn = readl(&pll->hfs_mfn);
170 mfd = readl(&pll->hfs_mfd);
171 op = readl(&pll->hfs_op);
173 mfn = readl(&pll->mfn);
174 mfd = readl(&pll->mfd);
175 op = readl(&pll->op);
178 mfd &= MXC_DPLLC_MFD_MFD_MASK;
179 mfn &= MXC_DPLLC_MFN_MFN_MASK;
180 pdf = op & MXC_DPLLC_OP_PDF_MASK;
181 mfi = MXC_DPLLC_OP_MFI_RD(op);
188 if (mfn >= 0x04000000) {
195 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
198 do_div(refclk, pdf + 1);
199 temp = refclk * mfn_abs;
200 do_div(temp, mfd + 1);
214 u32 get_mcu_main_clk(void)
218 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
219 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
220 return freq / (reg + 1);
224 * Get the rate of peripheral's root clock.
226 u32 get_periph_clk(void)
230 reg = readl(&mxc_ccm->cbcdr);
231 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
232 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
233 reg = readl(&mxc_ccm->cbcmr);
234 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
236 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
238 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
246 * Get the rate of ipg clock.
248 static u32 get_ipg_clk(void)
250 uint32_t freq, reg, div;
252 freq = get_ahb_clk();
254 reg = readl(&mxc_ccm->cbcdr);
255 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
261 * Get the rate of ipg_per clock.
263 static u32 get_ipg_per_clk(void)
265 u32 pred1, pred2, podf;
267 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
268 return get_ipg_clk();
269 /* Fixme: not handle what about lpm*/
270 podf = readl(&mxc_ccm->cbcdr);
271 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
272 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
273 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
274 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
278 * Get the rate of uart clk.
280 static u32 get_uart_clk(void)
282 unsigned int freq, reg, pred, podf;
284 reg = readl(&mxc_ccm->cscmr1);
285 switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
287 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
290 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
293 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
299 reg = readl(&mxc_ccm->cscdr1);
300 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
301 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
302 freq /= (pred + 1) * (podf + 1);
308 * This function returns the low power audio clock.
310 static u32 get_lp_apm(void)
313 u32 ccsr = readl(&mxc_ccm->ccsr);
315 if (((ccsr >> 9) & 1) == 0)
318 ret_val = MXC_CLK32 * 1024;
324 * get cspi clock rate.
326 static u32 imx_get_cspiclk(void)
328 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
329 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
330 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
332 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
333 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
334 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
338 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
339 ((pre_pdf + 1) * (pdf + 1));
342 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
343 ((pre_pdf + 1) * (pdf + 1));
346 ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
347 ((pre_pdf + 1) * (pdf + 1));
350 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
357 static u32 get_axi_a_clk(void)
359 u32 cbcdr = readl(&mxc_ccm->cbcdr);
360 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
362 return get_periph_clk() / (pdf + 1);
365 static u32 get_axi_b_clk(void)
367 u32 cbcdr = readl(&mxc_ccm->cbcdr);
368 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
370 return get_periph_clk() / (pdf + 1);
373 static u32 get_emi_slow_clk(void)
375 u32 cbcdr = readl(&mxc_ccm->cbcdr);
376 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
377 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
380 return get_ahb_clk() / (pdf + 1);
382 return get_periph_clk() / (pdf + 1);
385 static u32 get_ddr_clk(void)
388 u32 cbcmr = readl(&mxc_ccm->cbcmr);
389 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
391 u32 cbcdr = readl(&mxc_ccm->cbcdr);
392 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
393 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
395 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
396 ret_val /= ddr_clk_podf + 1;
401 switch (ddr_clk_sel) {
403 ret_val = get_axi_a_clk();
406 ret_val = get_axi_b_clk();
409 ret_val = get_emi_slow_clk();
412 ret_val = get_ahb_clk();
422 * The API of get mxc clocks.
424 unsigned int mxc_get_clock(enum mxc_clock clk)
428 return get_mcu_main_clk();
430 return get_ahb_clk();
432 return get_ipg_clk();
435 return get_ipg_per_clk();
437 return get_uart_clk();
439 return imx_get_cspiclk();
441 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
443 return get_ahb_clk();
445 return get_ddr_clk();
452 u32 imx_get_uartclk(void)
454 return get_uart_clk();
458 u32 imx_get_fecclk(void)
460 return mxc_get_clock(MXC_IPG_CLK);
463 static int gcd(int m, int n)
478 * This is to calculate various parameters based on reference clock and
479 * targeted clock based on the equation:
480 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
481 * This calculation is based on a fixed MFD value for simplicity.
483 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
485 u64 pd, mfi = 1, mfn, mfd, t1;
486 u32 n_target = target;
490 * Make sure targeted freq is in the valid range.
491 * Otherwise the following calculation might be wrong!!!
493 if (n_target < PLL_FREQ_MIN(ref) ||
494 n_target > PLL_FREQ_MAX(ref)) {
495 printf("Targeted peripheral clock should be"
496 "within [%d - %d]\n",
497 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
498 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
502 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
503 if (fixed_mfd[i].ref_clk_hz == ref) {
504 mfd = fixed_mfd[i].mfd;
509 if (i == ARRAY_SIZE(fixed_mfd))
512 /* Use n_target and n_ref to avoid overflow */
513 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
515 do_div(t1, (4 * n_ref));
517 if (mfi > PLL_MFI_MAX)
524 * Now got pd and mfi already
526 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
534 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
535 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
549 #define calc_div(tgt_clk, src_clk, limit) ({ \
551 if (((src_clk) % (tgt_clk)) <= 100) \
552 v = (src_clk) / (tgt_clk); \
554 v = ((src_clk) / (tgt_clk)) + 1;\
560 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
562 writel(0x1232, &pll->ctrl); \
563 writel(0x2, &pll->config); \
564 writel((((pd) - 1) << 0) | ((fi) << 4), \
566 writel(fn, &(pll->mfn)); \
567 writel((fd) - 1, &pll->mfd); \
568 writel((((pd) - 1) << 0) | ((fi) << 4), \
570 writel(fn, &pll->hfs_mfn); \
571 writel((fd) - 1, &pll->hfs_mfd); \
572 writel(0x1232, &pll->ctrl); \
573 while (!readl(&pll->ctrl) & 0x1) \
577 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
579 u32 ccsr = readl(&mxc_ccm->ccsr);
580 struct mxc_pll_reg *pll = mxc_plls[index];
584 /* Switch ARM to PLL2 clock */
585 writel(ccsr | 0x4, &mxc_ccm->ccsr);
586 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
587 pll_param->mfi, pll_param->mfn,
590 writel(ccsr & ~0x4, &mxc_ccm->ccsr);
593 /* Switch to pll2 bypass clock */
594 writel(ccsr | 0x2, &mxc_ccm->ccsr);
595 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
596 pll_param->mfi, pll_param->mfn,
599 writel(ccsr & ~0x2, &mxc_ccm->ccsr);
602 /* Switch to pll3 bypass clock */
603 writel(ccsr | 0x1, &mxc_ccm->ccsr);
604 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
605 pll_param->mfi, pll_param->mfn,
608 writel(ccsr & ~0x1, &mxc_ccm->ccsr);
611 /* Switch to pll4 bypass clock */
612 writel(ccsr | 0x20, &mxc_ccm->ccsr);
613 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
614 pll_param->mfi, pll_param->mfn,
617 writel(ccsr & ~0x20, &mxc_ccm->ccsr);
626 /* Config CPU clock */
627 static int config_core_clk(u32 ref, u32 freq)
630 struct pll_param pll_param;
632 memset(&pll_param, 0, sizeof(struct pll_param));
634 /* The case that periph uses PLL1 is not considered here */
635 ret = calc_pll_params(ref, freq, &pll_param);
637 printf("Error:Can't find pll parameters: %d\n", ret);
641 return config_pll_clk(PLL1_CLOCK, &pll_param);
644 static int config_nfc_clk(u32 nfc_clk)
646 u32 parent_rate = get_emi_slow_clk();
647 u32 div = parent_rate / nfc_clk;
653 if (parent_rate / div > NFC_CLK_MAX)
655 clrsetbits_le32(&mxc_ccm->cbcdr,
656 MXC_CCM_CBCDR_NFC_PODF_MASK,
657 MXC_CCM_CBCDR_NFC_PODF(div - 1));
658 while (readl(&mxc_ccm->cdhipr) != 0)
663 /* Config main_bus_clock for periphs */
664 static int config_periph_clk(u32 ref, u32 freq)
667 struct pll_param pll_param;
669 memset(&pll_param, 0, sizeof(struct pll_param));
671 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
672 ret = calc_pll_params(ref, freq, &pll_param);
674 printf("Error:Can't find pll parameters: %d\n",
678 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
679 readl(&mxc_ccm->cbcmr))) {
681 return config_pll_clk(PLL1_CLOCK, &pll_param);
684 return config_pll_clk(PLL3_CLOCK, &pll_param);
694 static int config_ddr_clk(u32 emi_clk)
697 s32 shift = 0, clk_sel, div = 1;
698 u32 cbcmr = readl(&mxc_ccm->cbcmr);
700 if (emi_clk > MAX_DDR_CLK) {
701 printf("Warning:DDR clock should not exceed %d MHz\n",
702 MAX_DDR_CLK / SZ_DEC_1M);
703 emi_clk = MAX_DDR_CLK;
706 clk_src = get_periph_clk();
707 /* Find DDR clock input */
708 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
726 if ((clk_src % emi_clk) < 10000000)
727 div = clk_src / emi_clk;
729 div = (clk_src / emi_clk) + 1;
733 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
734 while (readl(&mxc_ccm->cdhipr) != 0)
736 writel(0x0, &mxc_ccm->ccdr);
742 * This function assumes the expected core clock has to be changed by
743 * modifying the PLL. This is NOT true always but for most of the times,
744 * it is. So it assumes the PLL output freq is the same as the expected
745 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
746 * In the latter case, it will try to increase the presc value until
747 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
748 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
749 * on the targeted PLL and reference input clock to the PLL. Lastly,
750 * it sets the register based on these values along with the dividers.
751 * Note 1) There is no value checking for the passed-in divider values
752 * so the caller has to make sure those values are sensible.
753 * 2) Also adjust the NFC divider such that the NFC clock doesn't
754 * exceed NFC_CLK_MAX.
755 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
756 * 177MHz for higher voltage, this function fixes the max to 133MHz.
757 * 4) This function should not have allowed diag_printf() calls since
758 * the serial driver has been stoped. But leave then here to allow
759 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
761 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
767 if (config_core_clk(ref, freq))
771 if (config_periph_clk(ref, freq))
775 if (config_ddr_clk(freq))
779 if (config_nfc_clk(freq))
783 printf("Warning:Unsupported or invalid clock type\n");
791 * The clock for the external interface can be set to use internal clock
792 * if fuse bank 4, row 3, bit 2 is set.
793 * This is an undocumented feature and it was confirmed by Freescale's support:
794 * Fuses (but not pins) may be used to configure SATA clocks.
795 * Particularly the i.MX53 Fuse_Map contains the next information
796 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
797 * '00' - 100MHz (External)
798 * '01' - 50MHz (External)
799 * '10' - 120MHz, internal (USB PHY)
802 void mxc_set_sata_internal_clock(void)
805 (u32 *)(IIM_BASE_ADDR + 0x180c);
809 clrsetbits_le32(tmp_base, 0x6, 0x4);
814 * Dump some core clockes.
816 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
820 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
821 printf("PLL1 %8d MHz\n", freq / 1000000);
822 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
823 printf("PLL2 %8d MHz\n", freq / 1000000);
824 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
825 printf("PLL3 %8d MHz\n", freq / 1000000);
827 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
828 printf("PLL4 %8d MHz\n", freq / 1000000);
832 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
833 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
834 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
835 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
840 /***************************************************/
843 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,