2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/linkage.h>
11 #include <asm/armv7.h>
12 #include <asm/arch-armv7/generictimer.h>
15 #define RCPM_TWAITSR 0x04C
17 #define SCFG_CORE0_SFT_RST 0x130
18 #define SCFG_CORESRENCR 0x204
20 #define DCFG_CCSR_RSTCR 0x0B0
21 #define DCFG_CCSR_RSTCR_RESET_REQ 0x2
22 #define DCFG_CCSR_BRR 0x0E4
23 #define DCFG_CCSR_SCRATCHRW1 0x200
25 #define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
26 #define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
27 #define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
28 #define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
29 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
30 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
31 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
33 .pushsection ._secure.text, "ax"
39 #define ONE_MS (GENERIC_TIMER_CLK / 1000)
40 #define RESET_WAIT (30 * ONE_MS)
49 _ls102x_psci_supported_table:
50 .word ARM_PSCI_0_2_FN_PSCI_VERSION
51 .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
52 .word ARM_PSCI_0_2_FN_CPU_SUSPEND
53 .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
54 .word ARM_PSCI_0_2_FN_CPU_OFF
55 .word PSCI_FN_CPU_OFF_FEATURE_MASK
56 .word ARM_PSCI_0_2_FN_CPU_ON
57 .word PSCI_FN_CPU_ON_FEATURE_MASK
58 .word ARM_PSCI_0_2_FN_AFFINITY_INFO
59 .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
60 .word ARM_PSCI_0_2_FN_SYSTEM_OFF
61 .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
62 .word ARM_PSCI_0_2_FN_SYSTEM_RESET
63 .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
69 adr r2, _ls102x_psci_supported_table
81 @ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
82 @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
83 @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
84 @ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
85 LENTRY(psci_check_target_cpu_id)
86 @ Get the real CPU number
88 mov r0, #ARM_PSCI_RET_INVAL
90 @ Bit[31:24], bits must be zero.
94 @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
98 @ Affinity level 1 - Processors: should be in 0xf00 format.
103 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
107 mov r0, #ARM_PSCI_RET_SUCCESS
109 ENDPROC(psci_check_target_cpu_id)
115 push {r4, r5, r6, lr}
117 @ Clear and Get the correct CPU number
119 bl psci_check_target_cpu_id
120 cmp r0, #ARM_PSCI_RET_INVAL
125 bl psci_save_target_pc
128 @ Get DCFG base address
129 movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
130 movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
132 @ Detect target CPU state
133 ldr r2, [r4, #DCFG_CCSR_BRR]
140 @ Get SCFG base address
141 movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
142 movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
144 @ Enable CORE Soft Reset
148 str r5, [r0, #SCFG_CORESRENCR]
150 @ Get CPUx offset register
155 @ Do reset on target CPU
159 str r5, [r2, #SCFG_CORE0_SFT_RST]
162 timer_wait r2, RESET_WAIT
164 @ Disable CORE soft reset
166 str r5, [r0, #SCFG_CORESRENCR]
169 @ Release on target CPU
170 ldr r2, [r4, #DCFG_CCSR_BRR]
172 lsl r6, r6, r1 @ 32 bytes per CPU
176 str r2, [r4, #DCFG_CCSR_BRR]
178 @ Set secondary boot entry
179 ldr r6, =psci_cpu_entry
181 str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
187 mov r0, #ARM_PSCI_RET_SUCCESS
195 bl psci_cpu_off_common
200 .globl psci_affinity_info
204 mov r0, #ARM_PSCI_RET_INVAL
206 @ Verify Affinity level
208 bne out_affinity_info
210 bl psci_check_target_cpu_id
211 cmp r0, #ARM_PSCI_RET_INVAL
212 beq out_affinity_info
215 @ Get RCPM base address
216 movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
217 movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
219 mov r0, #PSCI_AFFINITY_LEVEL_ON
221 @ Detect target CPU state
222 ldr r2, [r4, #RCPM_TWAITSR]
226 beq out_affinity_info
228 mov r0, #PSCI_AFFINITY_LEVEL_OFF
233 .globl psci_system_reset
235 @ Get DCFG base address
236 movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
237 movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
239 mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
241 str r2, [r1, #DCFG_CCSR_RSTCR]