arch/arm/cpu/armv7/ls102xa/fdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <net.h>
   9 #include <asm/global_data.h>
  10 #include <linux/libfdt.h>
  11 #include <fdt_support.h>
  12 #include <asm/io.h>
  13 #include <asm/processor.h>
  14 #include <asm/arch/clock.h>
  15 #include <linux/ctype.h>
  16 #ifdef CONFIG_FSL_ESDHC
  17 #include <fsl_esdhc.h>
  18 #endif
  19 #include <tsec.h>
  20 #include <asm/arch/immap_ls102xa.h>
  21 #include <fsl_sec.h>
  22 #include <dm.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 void ft_fixup_enet_phy_connect_type(void *fdt)
  27 {
  28         struct udevice *dev;
  29         struct tsec_private *priv;
  30         const char *enet_path, *phy_path;
  31         char enet[16];
  32         char phy[16];
  33         int phy_node;
  34         int i = 0;
  35         uint32_t ph;
  36         char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
  37                           "ethernet@2d90000" };
  38
  39         for (; i < ARRAY_SIZE(name); i++) {
  40                 dev = eth_get_dev_by_name(name[i]);
  41                 if (dev) {
  42                         sprintf(enet, "ethernet%d", i);
  43                         sprintf(phy, "enet%d_rgmii_phy", i);
  44                 } else {
  45                         continue;
  46                 }
  47
  48                 priv = dev_get_priv(dev);
  49                 if (priv->flags & TSEC_SGMII)
  50                         continue;
  51
  52                 enet_path = fdt_get_alias(fdt, enet);
  53                 if (!enet_path)
  54                         continue;
  55
  56                 phy_path = fdt_get_alias(fdt, phy);
  57                 if (!phy_path)
  58                         continue;
  59
  60                 phy_node = fdt_path_offset(fdt, phy_path);
  61                 if (phy_node < 0)
  62                         continue;
  63
  64                 ph = fdt_create_phandle(fdt, phy_node);
  65                 if (ph)
  66                         do_fixup_by_path_u32(fdt, enet_path,
  67                                              "phy-handle", ph, 1);
  68
  69                 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  70                                  phy_string_for_interface(
  71                                  PHY_INTERFACE_MODE_RGMII_ID),
  72                                  strlen(phy_string_for_interface(
  73                                  PHY_INTERFACE_MODE_RGMII_ID)) + 1,
  74                                  1);
  75         }
  76 }
  77
  78 void ft_cpu_setup(void *blob, struct bd_info *bd)
  79 {
  80         int off;
  81         int val;
  82         const char *sysclk_path;
  83         struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
  84         unsigned int svr;
  85         svr = in_be32(&gur->svr);
  86
  87         unsigned long busclk = get_bus_freq(0);
  88
  89         /* delete crypto node if not on an E-processor */
  90         if (!IS_E_PROCESSOR(svr))
  91                 fdt_fixup_crypto_node(blob, 0);
  92 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  93         else {
  94                 ccsr_sec_t __iomem *sec;
  95
  96                 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
  97                 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  98         }
  99 #endif
 100
 101         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 102         while (off != -FDT_ERR_NOTFOUND) {
 103                 val = gd->cpu_clk;
 104                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 105                 off = fdt_node_offset_by_prop_value(blob, off,
 106                                                     "device_type", "cpu", 4);
 107         }
 108
 109         do_fixup_by_prop_u32(blob, "device_type", "soc",
 110                              4, "bus-frequency", busclk, 1);
 111
 112         ft_fixup_enet_phy_connect_type(blob);
 113
 114 #ifdef CONFIG_SYS_NS16550
 115         do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
 116                                "clock-frequency", CFG_SYS_NS16550_CLK, 1);
 117 #endif
 118
 119         sysclk_path = fdt_get_alias(blob, "sysclk");
 120         if (sysclk_path)
 121                 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
 122                                      get_board_sys_clk(), 1);
 123         do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
 124                                "clock-frequency", get_board_sys_clk(), 1);
 125
 126 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 127 #define UBOOT_HEAD_LEN  0x1000
 128         /*
 129          * Reserved memory in SD boot deep sleep case.
 130          * Second stage uboot binary and malloc space should be reserved.
 131          * If the memory they occupied has not been reserved, then this
 132          * space would be used by kernel and overwritten in uboot when
 133          * deep sleep resume, which cause deep sleep failed.
 134          * Since second uboot binary has a head, that space need to be
 135          * reserved either(assuming its size is less than 0x1000).
 136          */
 137         off = fdt_add_mem_rsv(blob, CONFIG_TEXT_BASE - UBOOT_HEAD_LEN,
 138                               CONFIG_SYS_MONITOR_LEN +
 139                               CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN);
 140         if (off < 0)
 141                 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
 142                        fdt_strerror(off));
 143 #endif
 144
 145 #if defined(CONFIG_FSL_ESDHC)
 146         fdt_fixup_esdhc(blob, bd);
 147 #endif
 148
 149         /*
 150          * platform bus clock = system bus clock/2
 151          * Here busclk = system bus clock
 152          * We are using the platform bus clock as 1588 Timer reference
 153          * clock source select
 154          */
 155         do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
 156                                "timer-frequency", busclk / 2, 1);
 157
 158         /*
 159          * clock-freq should change to clock-frequency and
 160          * flexcan-v1.0 should change to p1010-flexcan respectively
 161          * in the future.
 162          */
 163         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 164                                "clock_freq", busclk / 2, 1);
 165
 166         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 167                                "clock-frequency", busclk / 2, 1);
 168
 169         do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
 170                                "clock-frequency", busclk / 2, 1);
 171
 172 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 173         off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 174                                             CFG_SYS_IFC_ADDR);
 175         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 176 #else
 177         off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
 178                                             QSPI0_BASE_ADDR);
 179         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 180         off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
 181                                             DSPI1_BASE_ADDR);
 182         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 183 #endif
 184 }