1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
7 #include <clock_legacy.h>
9 #include <linux/libfdt.h>
10 #include <fdt_support.h>
12 #include <asm/processor.h>
13 #include <asm/arch/clock.h>
14 #include <linux/ctype.h>
15 #ifdef CONFIG_FSL_ESDHC
16 #include <fsl_esdhc.h>
19 #include <asm/arch/immap_ls102xa.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 void ft_fixup_enet_phy_connect_type(void *fdt)
30 struct eth_device *dev;
32 struct tsec_private *priv;
33 const char *enet_path, *phy_path;
40 char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
43 char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
46 for (; i < ARRAY_SIZE(name); i++) {
47 dev = eth_get_dev_by_name(name[i]);
49 sprintf(enet, "ethernet%d", i);
50 sprintf(phy, "enet%d_rgmii_phy", i);
56 if (priv->flags & TSEC_SGMII)
59 enet_path = fdt_get_alias(fdt, enet);
63 phy_path = fdt_get_alias(fdt, phy);
67 phy_node = fdt_path_offset(fdt, phy_path);
71 ph = fdt_create_phandle(fdt, phy_node);
73 do_fixup_by_path_u32(fdt, enet_path,
76 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
77 phy_string_for_interface(
78 PHY_INTERFACE_MODE_RGMII_ID),
79 strlen(phy_string_for_interface(
80 PHY_INTERFACE_MODE_RGMII_ID)) + 1,
85 void ft_cpu_setup(void *blob, bd_t *bd)
89 const char *sysclk_path;
90 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
92 svr = in_be32(&gur->svr);
94 unsigned long busclk = get_bus_freq(0);
96 /* delete crypto node if not on an E-processor */
97 if (!IS_E_PROCESSOR(svr))
98 fdt_fixup_crypto_node(blob, 0);
99 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
101 ccsr_sec_t __iomem *sec;
103 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
104 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
108 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
109 while (off != -FDT_ERR_NOTFOUND) {
111 fdt_setprop(blob, off, "clock-frequency", &val, 4);
112 off = fdt_node_offset_by_prop_value(blob, off,
113 "device_type", "cpu", 4);
116 do_fixup_by_prop_u32(blob, "device_type", "soc",
117 4, "bus-frequency", busclk, 1);
119 ft_fixup_enet_phy_connect_type(blob);
121 #ifdef CONFIG_SYS_NS16550
122 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
123 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
126 sysclk_path = fdt_get_alias(blob, "sysclk");
128 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
129 CONFIG_SYS_CLK_FREQ, 1);
130 do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
131 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
133 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
134 #define UBOOT_HEAD_LEN 0x1000
136 * Reserved memory in SD boot deep sleep case.
137 * Second stage uboot binary and malloc space should be reserved.
138 * If the memory they occupied has not been reserved, then this
139 * space would be used by kernel and overwritten in uboot when
140 * deep sleep resume, which cause deep sleep failed.
141 * Since second uboot binary has a head, that space need to be
142 * reserved either(assuming its size is less than 0x1000).
144 off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
145 CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
148 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
152 #if defined(CONFIG_FSL_ESDHC)
153 fdt_fixup_esdhc(blob, bd);
157 * platform bus clock = system bus clock/2
158 * Here busclk = system bus clock
159 * We are using the platform bus clock as 1588 Timer reference
160 * clock source select
162 do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
163 "timer-frequency", busclk / 2, 1);
166 * clock-freq should change to clock-frequency and
167 * flexcan-v1.0 should change to p1010-flexcan respectively
170 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
171 "clock_freq", busclk / 2, 1);
173 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
174 "clock-frequency", busclk / 2, 1);
176 do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
177 "clock-frequency", busclk / 2, 1);
179 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
180 off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
181 CONFIG_SYS_IFC_ADDR);
182 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
184 off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
186 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
187 off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
189 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);