3 select SYS_FSL_ERRATUM_A008378
4 select SYS_FSL_ERRATUM_A008407
5 select SYS_FSL_ERRATUM_A009663
6 select SYS_FSL_ERRATUM_A009942
7 select SYS_FSL_ERRATUM_A010315
10 select SYS_FSL_DDR_BE if SYS_FSL_DDR
11 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
12 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
13 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
14 select SYS_FSL_HAS_SEC
15 select SYS_FSL_SEC_COMPAT_5
18 menu "LS102xA architecture"
19 depends on ARCH_LS1021A
23 depends on ARCH_LS1021A
26 int "Maximum number of CPUs permitted for LS102xA"
27 depends on ARCH_LS1021A
30 Set this number to the maximum number of possible CPUs in the SoC.
31 SoCs may have multiple clusters with each cluster may have multiple
32 ports. If some ports are reserved but higher ports are used for
33 cores, count the reserved ports. This will allocate enough memory
34 in spin table to properly handle all cores.
36 config NUM_DDR_CONTROLLERS
37 int "Maximum DDR controllers"
43 Enable Freescale Secure Boot feature. Normally selected
44 by defconfig. If unsure, do not change.
46 config SYS_FSL_ERRATUM_A010315
47 bool "Workaround for PCIe erratum A010315"
58 config SYS_FSL_IFC_BANK_COUNT
59 int "Maximum banks of Integrated flash controller"
60 depends on ARCH_LS1021A
63 config SYS_FSL_ERRATUM_A008407