3 select SYS_FSL_DDR_BE if SYS_FSL_DDR
4 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
5 select SYS_FSL_ERRATUM_A008378
6 select SYS_FSL_ERRATUM_A008407
7 select SYS_FSL_ERRATUM_A008850
8 select SYS_FSL_ERRATUM_A008997
9 select SYS_FSL_ERRATUM_A009007
10 select SYS_FSL_ERRATUM_A009008
11 select SYS_FSL_ERRATUM_A009663
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A009942
14 select SYS_FSL_ERRATUM_A010315
15 select SYS_FSL_HAS_CCI400
16 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
17 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
18 select SYS_FSL_HAS_SEC
19 select SYS_FSL_SEC_COMPAT_5
27 menu "LS102xA architecture"
28 depends on ARCH_LS1021A
34 int "Maximum number of CPUs permitted for LS102xA"
37 Set this number to the maximum number of possible CPUs in the SoC.
38 SoCs may have multiple clusters with each cluster may have multiple
39 ports. If some ports are reserved but higher ports are used for
40 cores, count the reserved ports. This will allocate enough memory
41 in spin table to properly handle all cores.
46 Enable Freescale Secure Boot feature. Normally selected
47 by defconfig. If unsure, do not change.
49 config SYS_CCI400_OFFSET
50 hex "Offset for CCI400 base"
51 depends on SYS_FSL_HAS_CCI400
54 Offset for CCI400 base.
55 CCI400 base addr = CCSRBAR + CCI400_OFFSET
57 config SYS_FSL_ERRATUM_A008850
60 Workaround for DDR erratum A008850
62 config SYS_FSL_ERRATUM_A008997
65 Workaround for USB PHY erratum A008997
67 config SYS_FSL_ERRATUM_A009007
70 Workaround for USB PHY erratum A009007
72 config SYS_FSL_ERRATUM_A009008
75 Workaround for USB PHY erratum A009008
77 config SYS_FSL_ERRATUM_A009798
80 Workaround for USB PHY erratum A009798
82 config SYS_FSL_ERRATUM_A010315
83 bool "Workaround for PCIe erratum A010315"
85 config SYS_FSL_HAS_CCI400
97 config SYS_FSL_IFC_BANK_COUNT
98 int "Maximum banks of Integrated flash controller"
101 config SYS_FSL_ERRATUM_A008407