3 select SYS_FSL_ERRATUM_A010315
5 menu "LS102xA architecture"
6 depends on ARCH_LS1021A
10 depends on ARCH_LS1021A
13 int "Maximum number of CPUs permitted for LS102xA"
14 depends on ARCH_LS1021A
17 Set this number to the maximum number of possible CPUs in the SoC.
18 SoCs may have multiple clusters with each cluster may have multiple
19 ports. If some ports are reserved but higher ports are used for
20 cores, count the reserved ports. This will allocate enough memory
21 in spin table to properly handle all cores.
23 config SYS_FSL_ERRATUM_A010315
24 bool "Workaround for PCIe erratum A010315"
26 config SYS_FSL_IFC_BANK_COUNT
27 int "Maximum banks of Integrated flash controller"
28 depends on ARCH_LS1021A