2 * Clock initialization routines
4 * Copyright (c) 2011 The Chromium OS Authors.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __EXYNOS_CLOCK_INIT_H
10 #define __EXYNOS_CLOCK_INIT_H
13 MEM_TIMINGS_MSR_COUNT = 4,
16 /* These are the ratio's for configuring ARM clock */
17 struct arm_clk_ratios {
18 unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
26 unsigned pclk_dbg_ratio;
28 unsigned periph_ratio;
34 /* These are the memory timings for a particular memory type and speed */
36 enum mem_manuf mem_manuf; /* Memory manufacturer */
37 enum ddr_mode mem_type; /* Memory type */
38 unsigned frequency_mhz; /* Frequency of memory in MHz */
40 /* Here follow the timing parameters for the selected memory */
62 unsigned pclk_cdrex_ratio;
63 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
68 unsigned timing_power;
70 /* DQS, DQ, DEBUG offsets */
77 unsigned phy0_pulld_dqs;
78 unsigned phy1_pulld_dqs;
80 unsigned lpddr3_ctrl_phy_reset;
81 unsigned ctrl_start_point;
93 unsigned dfi_init_start;
99 unsigned zq_mode_term;
100 unsigned zq_mode_noterm; /* 1 to allow termination disable */
105 unsigned membaseconfig0;
106 unsigned membaseconfig1;
107 unsigned prechconfig_tp_cnt;
111 /* Channel and Chip Selection */
112 uint8_t dmc_channels; /* number of memory channels */
113 uint8_t chips_per_channel; /* number of chips per channel */
114 uint8_t chips_to_configure; /* number of chips to configure */
115 uint8_t send_zq_init; /* 1 to send this command */
116 unsigned impedance; /* drive strength impedeance */
117 uint8_t gate_leveling_enable; /* check gate leveling is enabled */
121 * Get the correct memory timings for our selected memory type and speed.
123 * This function can be called from SPL or the main U-Boot.
125 * @return pointer to the memory timings that we should use
127 struct mem_timings *clock_get_mem_timings(void);
130 * Initialize clock for the device
132 void system_clock_init(void);
135 * Set clock divisor value for booting from EMMC.
137 void emmc_boot_clk_div_set(void);