2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/periph.h>
31 * This structure is to store the src bit, div bit and prediv bit
32 * positions of the peripheral clocks of the src and div registers
40 /* src_bit div_bit prediv_bit */
41 static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
73 /* Epll Clock division values to achive different frequency output */
74 static struct set_epll_con_val exynos5_epll_div[] = {
75 { 192000000, 0, 48, 3, 1, 0 },
76 { 180000000, 0, 45, 3, 1, 0 },
77 { 73728000, 1, 73, 3, 3, 47710 },
78 { 67737600, 1, 90, 4, 3, 20762 },
79 { 49152000, 0, 49, 3, 3, 9961 },
80 { 45158400, 0, 45, 3, 3, 10381 },
81 { 180633600, 0, 45, 3, 1, 10381 }
84 /* exynos: return pll clock frequency */
85 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
87 unsigned long m, p, s = 0, mask, fout;
90 * APLL_CON: MIDV [25:16]
91 * MPLL_CON: MIDV [25:16]
92 * EPLL_CON: MIDV [24:16]
93 * VPLL_CON: MIDV [24:16]
94 * BPLL_CON: MIDV [25:16]: Exynos5
96 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
101 m = (r >> 16) & mask;
108 freq = CONFIG_SYS_CLK_FREQ;
110 if (pllreg == EPLL) {
112 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
113 fout = (m + k / 65536) * (freq / (p * (1 << s)));
114 } else if (pllreg == VPLL) {
116 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
117 fout = (m + k / 1024) * (freq / (p * (1 << s)));
121 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
122 fout = m * (freq / (p * (1 << (s - 1))));
128 /* exynos4: return pll clock frequency */
129 static unsigned long exynos4_get_pll_clk(int pllreg)
131 struct exynos4_clock *clk =
132 (struct exynos4_clock *)samsung_get_base_clock();
133 unsigned long r, k = 0;
137 r = readl(&clk->apll_con0);
140 r = readl(&clk->mpll_con0);
143 r = readl(&clk->epll_con0);
144 k = readl(&clk->epll_con1);
147 r = readl(&clk->vpll_con0);
148 k = readl(&clk->vpll_con1);
151 printf("Unsupported PLL (%d)\n", pllreg);
155 return exynos_get_pll_clk(pllreg, r, k);
158 /* exynos4x12: return pll clock frequency */
159 static unsigned long exynos4x12_get_pll_clk(int pllreg)
161 struct exynos4x12_clock *clk =
162 (struct exynos4x12_clock *)samsung_get_base_clock();
163 unsigned long r, k = 0;
167 r = readl(&clk->apll_con0);
170 r = readl(&clk->mpll_con0);
173 r = readl(&clk->epll_con0);
174 k = readl(&clk->epll_con1);
177 r = readl(&clk->vpll_con0);
178 k = readl(&clk->vpll_con1);
181 printf("Unsupported PLL (%d)\n", pllreg);
185 return exynos_get_pll_clk(pllreg, r, k);
188 /* exynos5: return pll clock frequency */
189 static unsigned long exynos5_get_pll_clk(int pllreg)
191 struct exynos5_clock *clk =
192 (struct exynos5_clock *)samsung_get_base_clock();
193 unsigned long r, k = 0, fout;
194 unsigned int pll_div2_sel, fout_sel;
198 r = readl(&clk->apll_con0);
201 r = readl(&clk->mpll_con0);
204 r = readl(&clk->epll_con0);
205 k = readl(&clk->epll_con1);
208 r = readl(&clk->vpll_con0);
209 k = readl(&clk->vpll_con1);
212 r = readl(&clk->bpll_con0);
215 printf("Unsupported PLL (%d)\n", pllreg);
219 fout = exynos_get_pll_clk(pllreg, r, k);
221 /* According to the user manual, in EVT1 MPLL and BPLL always gives
222 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
223 if (pllreg == MPLL || pllreg == BPLL) {
224 pll_div2_sel = readl(&clk->pll_div2_sel);
228 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
229 & MPLL_FOUT_SEL_MASK;
232 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
233 & BPLL_FOUT_SEL_MASK;
247 static unsigned long exynos5_get_periph_rate(int peripheral)
249 struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
250 unsigned long sclk, sub_clk;
251 unsigned int src, div, sub_div;
252 struct exynos5_clock *clk =
253 (struct exynos5_clock *)samsung_get_base_clock();
255 switch (peripheral) {
256 case PERIPH_ID_UART0:
257 case PERIPH_ID_UART1:
258 case PERIPH_ID_UART2:
259 case PERIPH_ID_UART3:
260 src = readl(&clk->src_peric0);
261 div = readl(&clk->div_peric0);
268 src = readl(&clk->src_peric0);
269 div = readl(&clk->div_peric3);
273 src = readl(&clk->src_peric1);
274 div = readl(&clk->div_peric1);
277 src = readl(&clk->src_peric1);
278 div = readl(&clk->div_peric2);
282 src = readl(&clk->sclk_src_isp);
283 div = readl(&clk->sclk_div_isp);
285 case PERIPH_ID_SDMMC0:
286 case PERIPH_ID_SDMMC1:
287 case PERIPH_ID_SDMMC2:
288 case PERIPH_ID_SDMMC3:
289 src = readl(&clk->src_fsys);
290 div = readl(&clk->div_fsys1);
300 sclk = exynos5_get_pll_clk(MPLL);
301 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
303 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
305 return (sclk / sub_div) / div;
307 debug("%s: invalid peripheral %d", __func__, peripheral);
311 src = (src >> bit_info->src_bit) & 0xf;
314 case EXYNOS_SRC_MPLL:
315 sclk = exynos5_get_pll_clk(MPLL);
317 case EXYNOS_SRC_EPLL:
318 sclk = exynos5_get_pll_clk(EPLL);
320 case EXYNOS_SRC_VPLL:
321 sclk = exynos5_get_pll_clk(VPLL);
327 /* Ratio clock division for this peripheral */
328 sub_div = (div >> bit_info->div_bit) & 0xf;
329 sub_clk = sclk / (sub_div + 1);
331 /* Pre-ratio clock division for SDMMC0 and 2 */
332 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
333 div = (div >> bit_info->prediv_bit) & 0xff;
334 return sub_clk / (div + 1);
340 unsigned long clock_get_periph_rate(int peripheral)
342 if (cpu_is_exynos5())
343 return exynos5_get_periph_rate(peripheral);
348 /* exynos4: return ARM clock frequency */
349 static unsigned long exynos4_get_arm_clk(void)
351 struct exynos4_clock *clk =
352 (struct exynos4_clock *)samsung_get_base_clock();
354 unsigned long armclk;
355 unsigned int core_ratio;
356 unsigned int core2_ratio;
358 div = readl(&clk->div_cpu0);
360 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
361 core_ratio = (div >> 0) & 0x7;
362 core2_ratio = (div >> 28) & 0x7;
364 armclk = get_pll_clk(APLL) / (core_ratio + 1);
365 armclk /= (core2_ratio + 1);
370 /* exynos4x12: return ARM clock frequency */
371 static unsigned long exynos4x12_get_arm_clk(void)
373 struct exynos4x12_clock *clk =
374 (struct exynos4x12_clock *)samsung_get_base_clock();
376 unsigned long armclk;
377 unsigned int core_ratio;
378 unsigned int core2_ratio;
380 div = readl(&clk->div_cpu0);
382 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
383 core_ratio = (div >> 0) & 0x7;
384 core2_ratio = (div >> 28) & 0x7;
386 armclk = get_pll_clk(APLL) / (core_ratio + 1);
387 armclk /= (core2_ratio + 1);
392 /* exynos5: return ARM clock frequency */
393 static unsigned long exynos5_get_arm_clk(void)
395 struct exynos5_clock *clk =
396 (struct exynos5_clock *)samsung_get_base_clock();
398 unsigned long armclk;
399 unsigned int arm_ratio;
400 unsigned int arm2_ratio;
402 div = readl(&clk->div_cpu0);
404 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
405 arm_ratio = (div >> 0) & 0x7;
406 arm2_ratio = (div >> 28) & 0x7;
408 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
409 armclk /= (arm2_ratio + 1);
414 /* exynos4: return pwm clock frequency */
415 static unsigned long exynos4_get_pwm_clk(void)
417 struct exynos4_clock *clk =
418 (struct exynos4_clock *)samsung_get_base_clock();
419 unsigned long pclk, sclk;
423 if (s5p_get_cpu_rev() == 0) {
428 sel = readl(&clk->src_peril0);
429 sel = (sel >> 24) & 0xf;
432 sclk = get_pll_clk(MPLL);
434 sclk = get_pll_clk(EPLL);
436 sclk = get_pll_clk(VPLL);
444 ratio = readl(&clk->div_peril3);
446 } else if (s5p_get_cpu_rev() == 1) {
447 sclk = get_pll_clk(MPLL);
452 pclk = sclk / (ratio + 1);
457 /* exynos4x12: return pwm clock frequency */
458 static unsigned long exynos4x12_get_pwm_clk(void)
460 unsigned long pclk, sclk;
463 sclk = get_pll_clk(MPLL);
466 pclk = sclk / (ratio + 1);
471 /* exynos4: return uart clock frequency */
472 static unsigned long exynos4_get_uart_clk(int dev_index)
474 struct exynos4_clock *clk =
475 (struct exynos4_clock *)samsung_get_base_clock();
476 unsigned long uclk, sclk;
489 sel = readl(&clk->src_peril0);
490 sel = (sel >> (dev_index << 2)) & 0xf;
493 sclk = get_pll_clk(MPLL);
495 sclk = get_pll_clk(EPLL);
497 sclk = get_pll_clk(VPLL);
506 * UART3_RATIO [12:15]
507 * UART4_RATIO [16:19]
508 * UART5_RATIO [23:20]
510 ratio = readl(&clk->div_peril0);
511 ratio = (ratio >> (dev_index << 2)) & 0xf;
513 uclk = sclk / (ratio + 1);
518 /* exynos4x12: return uart clock frequency */
519 static unsigned long exynos4x12_get_uart_clk(int dev_index)
521 struct exynos4x12_clock *clk =
522 (struct exynos4x12_clock *)samsung_get_base_clock();
523 unsigned long uclk, sclk;
535 sel = readl(&clk->src_peril0);
536 sel = (sel >> (dev_index << 2)) & 0xf;
539 sclk = get_pll_clk(MPLL);
541 sclk = get_pll_clk(EPLL);
543 sclk = get_pll_clk(VPLL);
552 * UART3_RATIO [12:15]
553 * UART4_RATIO [16:19]
555 ratio = readl(&clk->div_peril0);
556 ratio = (ratio >> (dev_index << 2)) & 0xf;
558 uclk = sclk / (ratio + 1);
563 /* exynos5: return uart clock frequency */
564 static unsigned long exynos5_get_uart_clk(int dev_index)
566 struct exynos5_clock *clk =
567 (struct exynos5_clock *)samsung_get_base_clock();
568 unsigned long uclk, sclk;
581 sel = readl(&clk->src_peric0);
582 sel = (sel >> (dev_index << 2)) & 0xf;
585 sclk = get_pll_clk(MPLL);
587 sclk = get_pll_clk(EPLL);
589 sclk = get_pll_clk(VPLL);
598 * UART3_RATIO [12:15]
599 * UART4_RATIO [16:19]
600 * UART5_RATIO [23:20]
602 ratio = readl(&clk->div_peric0);
603 ratio = (ratio >> (dev_index << 2)) & 0xf;
605 uclk = sclk / (ratio + 1);
610 static unsigned long exynos4_get_mmc_clk(int dev_index)
612 struct exynos4_clock *clk =
613 (struct exynos4_clock *)samsung_get_base_clock();
614 unsigned long uclk, sclk;
615 unsigned int sel, ratio, pre_ratio;
618 sel = readl(&clk->src_fsys);
619 sel = (sel >> (dev_index << 2)) & 0xf;
622 sclk = get_pll_clk(MPLL);
624 sclk = get_pll_clk(EPLL);
626 sclk = get_pll_clk(VPLL);
633 ratio = readl(&clk->div_fsys1);
634 pre_ratio = readl(&clk->div_fsys1);
638 ratio = readl(&clk->div_fsys2);
639 pre_ratio = readl(&clk->div_fsys2);
642 ratio = readl(&clk->div_fsys3);
643 pre_ratio = readl(&clk->div_fsys3);
649 if (dev_index == 1 || dev_index == 3)
652 ratio = (ratio >> shift) & 0xf;
653 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
654 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
659 static unsigned long exynos5_get_mmc_clk(int dev_index)
661 struct exynos5_clock *clk =
662 (struct exynos5_clock *)samsung_get_base_clock();
663 unsigned long uclk, sclk;
664 unsigned int sel, ratio, pre_ratio;
667 sel = readl(&clk->src_fsys);
668 sel = (sel >> (dev_index << 2)) & 0xf;
671 sclk = get_pll_clk(MPLL);
673 sclk = get_pll_clk(EPLL);
675 sclk = get_pll_clk(VPLL);
682 ratio = readl(&clk->div_fsys1);
683 pre_ratio = readl(&clk->div_fsys1);
687 ratio = readl(&clk->div_fsys2);
688 pre_ratio = readl(&clk->div_fsys2);
694 if (dev_index == 1 || dev_index == 3)
697 ratio = (ratio >> shift) & 0xf;
698 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
699 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
704 /* exynos4: set the mmc clock */
705 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
707 struct exynos4_clock *clk =
708 (struct exynos4_clock *)samsung_get_base_clock();
714 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
716 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
718 * MMC4_PRE_RATIO [15:8]
721 addr = (unsigned int)&clk->div_fsys1;
722 } else if (dev_index == 4) {
723 addr = (unsigned int)&clk->div_fsys3;
726 addr = (unsigned int)&clk->div_fsys2;
731 val &= ~(0xff << ((dev_index << 4) + 8));
732 val |= (div & 0xff) << ((dev_index << 4) + 8);
736 /* exynos4x12: set the mmc clock */
737 static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
739 struct exynos4x12_clock *clk =
740 (struct exynos4x12_clock *)samsung_get_base_clock();
746 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
748 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
751 addr = (unsigned int)&clk->div_fsys1;
753 addr = (unsigned int)&clk->div_fsys2;
758 val &= ~(0xff << ((dev_index << 4) + 8));
759 val |= (div & 0xff) << ((dev_index << 4) + 8);
763 /* exynos5: set the mmc clock */
764 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
766 struct exynos5_clock *clk =
767 (struct exynos5_clock *)samsung_get_base_clock();
773 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
775 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
778 addr = (unsigned int)&clk->div_fsys1;
780 addr = (unsigned int)&clk->div_fsys2;
785 val &= ~(0xff << ((dev_index << 4) + 8));
786 val |= (div & 0xff) << ((dev_index << 4) + 8);
790 /* get_lcd_clk: return lcd clock frequency */
791 static unsigned long exynos4_get_lcd_clk(void)
793 struct exynos4_clock *clk =
794 (struct exynos4_clock *)samsung_get_base_clock();
795 unsigned long pclk, sclk;
803 sel = readl(&clk->src_lcd0);
812 sclk = get_pll_clk(MPLL);
814 sclk = get_pll_clk(EPLL);
816 sclk = get_pll_clk(VPLL);
824 ratio = readl(&clk->div_lcd0);
827 pclk = sclk / (ratio + 1);
832 /* get_lcd_clk: return lcd clock frequency */
833 static unsigned long exynos5_get_lcd_clk(void)
835 struct exynos5_clock *clk =
836 (struct exynos5_clock *)samsung_get_base_clock();
837 unsigned long pclk, sclk;
845 sel = readl(&clk->src_disp1_0);
854 sclk = get_pll_clk(MPLL);
856 sclk = get_pll_clk(EPLL);
858 sclk = get_pll_clk(VPLL);
866 ratio = readl(&clk->div_disp1_0);
869 pclk = sclk / (ratio + 1);
874 void exynos4_set_lcd_clk(void)
876 struct exynos4_clock *clk =
877 (struct exynos4_clock *)samsung_get_base_clock();
878 unsigned int cfg = 0;
890 cfg = readl(&clk->gate_block);
892 writel(cfg, &clk->gate_block);
898 * MDNIE_PWM0_SEL [8:11]
900 * set lcd0 src clock 0x6: SCLK_MPLL
902 cfg = readl(&clk->src_lcd0);
905 writel(cfg, &clk->src_lcd0);
915 * Gating all clocks for FIMD0
917 cfg = readl(&clk->gate_ip_lcd0);
919 writel(cfg, &clk->gate_ip_lcd0);
925 * MDNIE_PWM0_RATIO [11:8]
926 * MDNIE_PWM_PRE_RATIO [15:12]
927 * MIPI0_RATIO [19:16]
928 * MIPI0_PRE_RATIO [23:20]
933 writel(cfg, &clk->div_lcd0);
936 void exynos5_set_lcd_clk(void)
938 struct exynos5_clock *clk =
939 (struct exynos5_clock *)samsung_get_base_clock();
940 unsigned int cfg = 0;
952 cfg = readl(&clk->gate_block);
954 writel(cfg, &clk->gate_block);
960 * MDNIE_PWM0_SEL [8:11]
962 * set lcd0 src clock 0x6: SCLK_MPLL
964 cfg = readl(&clk->src_disp1_0);
967 writel(cfg, &clk->src_disp1_0);
977 * Gating all clocks for FIMD0
979 cfg = readl(&clk->gate_ip_disp1);
981 writel(cfg, &clk->gate_ip_disp1);
987 * MDNIE_PWM0_RATIO [11:8]
988 * MDNIE_PWM_PRE_RATIO [15:12]
989 * MIPI0_RATIO [19:16]
990 * MIPI0_PRE_RATIO [23:20]
995 writel(cfg, &clk->div_disp1_0);
998 void exynos4_set_mipi_clk(void)
1000 struct exynos4_clock *clk =
1001 (struct exynos4_clock *)samsung_get_base_clock();
1002 unsigned int cfg = 0;
1008 * MDNIE_PWM0_SEL [8:11]
1010 * set mipi0 src clock 0x6: SCLK_MPLL
1012 cfg = readl(&clk->src_lcd0);
1013 cfg &= ~(0xf << 12);
1015 writel(cfg, &clk->src_lcd0);
1021 * MDNIE_PWM0_MASK [8]
1023 * set src mask mipi0 0x1: Unmask
1025 cfg = readl(&clk->src_mask_lcd0);
1027 writel(cfg, &clk->src_mask_lcd0);
1037 * Gating all clocks for MIPI0
1039 cfg = readl(&clk->gate_ip_lcd0);
1041 writel(cfg, &clk->gate_ip_lcd0);
1046 * MDNIE0_RATIO [7:4]
1047 * MDNIE_PWM0_RATIO [11:8]
1048 * MDNIE_PWM_PRE_RATIO [15:12]
1049 * MIPI0_RATIO [19:16]
1050 * MIPI0_PRE_RATIO [23:20]
1053 cfg &= ~(0xf << 16);
1055 writel(cfg, &clk->div_lcd0);
1061 * exynos5: obtaining the I2C clock
1063 static unsigned long exynos5_get_i2c_clk(void)
1065 struct exynos5_clock *clk =
1066 (struct exynos5_clock *)samsung_get_base_clock();
1067 unsigned long aclk_66, aclk_66_pre, sclk;
1070 sclk = get_pll_clk(MPLL);
1072 ratio = (readl(&clk->div_top1)) >> 24;
1074 aclk_66_pre = sclk / (ratio + 1);
1075 ratio = readl(&clk->div_top0);
1077 aclk_66 = aclk_66_pre / (ratio + 1);
1081 int exynos5_set_epll_clk(unsigned long rate)
1083 unsigned int epll_con, epll_con_k;
1085 unsigned int lockcnt;
1087 struct exynos5_clock *clk =
1088 (struct exynos5_clock *)samsung_get_base_clock();
1090 epll_con = readl(&clk->epll_con0);
1091 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1092 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1093 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1094 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1095 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1097 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1098 if (exynos5_epll_div[i].freq_out == rate)
1102 if (i == ARRAY_SIZE(exynos5_epll_div))
1105 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1106 epll_con |= exynos5_epll_div[i].en_lock_det <<
1107 EPLL_CON0_LOCK_DET_EN_SHIFT;
1108 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1109 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1110 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1113 * Required period ( in cycles) to genarate a stable clock output.
1114 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1115 * frequency input (as per spec)
1117 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1119 writel(lockcnt, &clk->epll_lock);
1120 writel(epll_con, &clk->epll_con0);
1121 writel(epll_con_k, &clk->epll_con1);
1123 start = get_timer(0);
1125 while (!(readl(&clk->epll_con0) &
1126 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1127 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1128 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1135 void exynos5_set_i2s_clk_source(void)
1137 struct exynos5_clock *clk =
1138 (struct exynos5_clock *)samsung_get_base_clock();
1140 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1141 (CLK_SRC_SCLK_EPLL));
1144 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1145 unsigned int dst_frq)
1147 struct exynos5_clock *clk =
1148 (struct exynos5_clock *)samsung_get_base_clock();
1151 if ((dst_frq == 0) || (src_frq == 0)) {
1152 debug("%s: Invalid requency input for prescaler\n", __func__);
1153 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1157 div = (src_frq / dst_frq);
1158 if (div > AUDIO_1_RATIO_MASK) {
1159 debug("%s: Frequency ratio is out of range\n", __func__);
1160 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1163 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1164 (div & AUDIO_1_RATIO_MASK));
1169 * Linearly searches for the most accurate main and fine stage clock scalars
1170 * (divisors) for a specified target frequency and scalar bit sizes by checking
1171 * all multiples of main_scalar_bits values. Will always return scalars up to or
1172 * slower than target.
1174 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1175 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1176 * @param input_freq Clock frequency to be scaled in Hz
1177 * @param target_freq Desired clock frequency in Hz
1178 * @param best_fine_scalar Pointer to store the fine stage divisor
1180 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1183 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1184 unsigned int fine_scalar_bits, unsigned int input_rate,
1185 unsigned int target_rate, unsigned int *best_fine_scalar)
1188 int best_main_scalar = -1;
1189 unsigned int best_error = target_rate;
1190 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1191 const unsigned int loops = 1 << main_scaler_bits;
1193 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1196 assert(best_fine_scalar != NULL);
1197 assert(main_scaler_bits <= fine_scalar_bits);
1199 *best_fine_scalar = 1;
1201 if (input_rate == 0 || target_rate == 0)
1204 if (target_rate >= input_rate)
1207 for (i = 1; i <= loops; i++) {
1208 const unsigned int effective_div = max(min(input_rate / i /
1209 target_rate, cap), 1);
1210 const unsigned int effective_rate = input_rate / i /
1212 const int error = target_rate - effective_rate;
1214 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1215 effective_rate, error);
1217 if (error >= 0 && error <= best_error) {
1219 best_main_scalar = i;
1220 *best_fine_scalar = effective_div;
1224 return best_main_scalar;
1227 static int exynos5_set_spi_clk(enum periph_id periph_id,
1230 struct exynos5_clock *clk =
1231 (struct exynos5_clock *)samsung_get_base_clock();
1234 unsigned shift, pre_shift;
1235 unsigned mask = 0xff;
1238 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1240 debug("%s: Cannot set clock rate for periph %d",
1241 __func__, periph_id);
1247 switch (periph_id) {
1248 case PERIPH_ID_SPI0:
1249 reg = &clk->div_peric1;
1253 case PERIPH_ID_SPI1:
1254 reg = &clk->div_peric1;
1258 case PERIPH_ID_SPI2:
1259 reg = &clk->div_peric2;
1263 case PERIPH_ID_SPI3:
1264 reg = &clk->sclk_div_isp;
1268 case PERIPH_ID_SPI4:
1269 reg = &clk->sclk_div_isp;
1274 debug("%s: Unsupported peripheral ID %d\n", __func__,
1278 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1279 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1284 static unsigned long exynos4_get_i2c_clk(void)
1286 struct exynos4_clock *clk =
1287 (struct exynos4_clock *)samsung_get_base_clock();
1288 unsigned long sclk, aclk_100;
1291 sclk = get_pll_clk(APLL);
1293 ratio = (readl(&clk->div_top)) >> 4;
1295 aclk_100 = sclk / (ratio + 1);
1299 unsigned long get_pll_clk(int pllreg)
1301 if (cpu_is_exynos5())
1302 return exynos5_get_pll_clk(pllreg);
1304 if (proid_is_exynos4412())
1305 return exynos4x12_get_pll_clk(pllreg);
1306 return exynos4_get_pll_clk(pllreg);
1310 unsigned long get_arm_clk(void)
1312 if (cpu_is_exynos5())
1313 return exynos5_get_arm_clk();
1315 if (proid_is_exynos4412())
1316 return exynos4x12_get_arm_clk();
1317 return exynos4_get_arm_clk();
1321 unsigned long get_i2c_clk(void)
1323 if (cpu_is_exynos5()) {
1324 return exynos5_get_i2c_clk();
1325 } else if (cpu_is_exynos4()) {
1326 return exynos4_get_i2c_clk();
1328 debug("I2C clock is not set for this CPU\n");
1333 unsigned long get_pwm_clk(void)
1335 if (cpu_is_exynos5())
1336 return clock_get_periph_rate(PERIPH_ID_PWM0);
1338 if (proid_is_exynos4412())
1339 return exynos4x12_get_pwm_clk();
1340 return exynos4_get_pwm_clk();
1344 unsigned long get_uart_clk(int dev_index)
1346 if (cpu_is_exynos5())
1347 return exynos5_get_uart_clk(dev_index);
1349 if (proid_is_exynos4412())
1350 return exynos4x12_get_uart_clk(dev_index);
1351 return exynos4_get_uart_clk(dev_index);
1355 unsigned long get_mmc_clk(int dev_index)
1357 if (cpu_is_exynos5())
1358 return exynos5_get_mmc_clk(dev_index);
1360 return exynos4_get_mmc_clk(dev_index);
1363 void set_mmc_clk(int dev_index, unsigned int div)
1365 if (cpu_is_exynos5())
1366 exynos5_set_mmc_clk(dev_index, div);
1368 if (proid_is_exynos4412())
1369 exynos4x12_set_mmc_clk(dev_index, div);
1370 exynos4_set_mmc_clk(dev_index, div);
1374 unsigned long get_lcd_clk(void)
1376 if (cpu_is_exynos4())
1377 return exynos4_get_lcd_clk();
1379 return exynos5_get_lcd_clk();
1382 void set_lcd_clk(void)
1384 if (cpu_is_exynos4())
1385 exynos4_set_lcd_clk();
1387 exynos5_set_lcd_clk();
1390 void set_mipi_clk(void)
1392 if (cpu_is_exynos4())
1393 exynos4_set_mipi_clk();
1396 int set_spi_clk(int periph_id, unsigned int rate)
1398 if (cpu_is_exynos5())
1399 return exynos5_set_spi_clk(periph_id, rate);
1404 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
1407 if (cpu_is_exynos5())
1408 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
1413 void set_i2s_clk_source(void)
1415 if (cpu_is_exynos5())
1416 exynos5_set_i2s_clk_source();
1419 int set_epll_clk(unsigned long rate)
1421 if (cpu_is_exynos5())
1422 return exynos5_set_epll_clk(rate);