arch/arm/cpu/armv7/exynos/clock.c

   1 /*
   2  * Copyright (C) 2010 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/clk.h>
  28
  29 /* exynos: return pll clock frequency */
  30 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
  31 {
  32         unsigned long m, p, s = 0, mask, fout;
  33         unsigned int freq;
  34         /*
  35          * APLL_CON: MIDV [25:16]
  36          * MPLL_CON: MIDV [25:16]
  37          * EPLL_CON: MIDV [24:16]
  38          * VPLL_CON: MIDV [24:16]
  39          * BPLL_CON: MIDV [25:16]: Exynos5
  40          */
  41         if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
  42                 mask = 0x3ff;
  43         else
  44                 mask = 0x1ff;
  45
  46         m = (r >> 16) & mask;
  47
  48         /* PDIV [13:8] */
  49         p = (r >> 8) & 0x3f;
  50         /* SDIV [2:0] */
  51         s = r & 0x7;
  52
  53         freq = CONFIG_SYS_CLK_FREQ;
  54
  55         if (pllreg == EPLL) {
  56                 k = k & 0xffff;
  57                 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
  58                 fout = (m + k / 65536) * (freq / (p * (1 << s)));
  59         } else if (pllreg == VPLL) {
  60                 k = k & 0xfff;
  61                 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
  62                 fout = (m + k / 1024) * (freq / (p * (1 << s)));
  63         } else {
  64                 if (s < 1)
  65                         s = 1;
  66                 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
  67                 fout = m * (freq / (p * (1 << (s - 1))));
  68         }
  69
  70         return fout;
  71 }
  72
  73 /* exynos4: return pll clock frequency */
  74 static unsigned long exynos4_get_pll_clk(int pllreg)
  75 {
  76         struct exynos4_clock *clk =
  77                 (struct exynos4_clock *)samsung_get_base_clock();
  78         unsigned long r, k = 0;
  79
  80         switch (pllreg) {
  81         case APLL:
  82                 r = readl(&clk->apll_con0);
  83                 break;
  84         case MPLL:
  85                 r = readl(&clk->mpll_con0);
  86                 break;
  87         case EPLL:
  88                 r = readl(&clk->epll_con0);
  89                 k = readl(&clk->epll_con1);
  90                 break;
  91         case VPLL:
  92                 r = readl(&clk->vpll_con0);
  93                 k = readl(&clk->vpll_con1);
  94                 break;
  95         default:
  96                 printf("Unsupported PLL (%d)\n", pllreg);
  97                 return 0;
  98         }
  99
 100         return exynos_get_pll_clk(pllreg, r, k);
 101 }
 102
 103 /* exynos5: return pll clock frequency */
 104 static unsigned long exynos5_get_pll_clk(int pllreg)
 105 {
 106         struct exynos5_clock *clk =
 107                 (struct exynos5_clock *)samsung_get_base_clock();
 108         unsigned long r, k = 0, fout;
 109         unsigned int pll_div2_sel, fout_sel;
 110
 111         switch (pllreg) {
 112         case APLL:
 113                 r = readl(&clk->apll_con0);
 114                 break;
 115         case MPLL:
 116                 r = readl(&clk->mpll_con0);
 117                 break;
 118         case EPLL:
 119                 r = readl(&clk->epll_con0);
 120                 k = readl(&clk->epll_con1);
 121                 break;
 122         case VPLL:
 123                 r = readl(&clk->vpll_con0);
 124                 k = readl(&clk->vpll_con1);
 125                 break;
 126         case BPLL:
 127                 r = readl(&clk->bpll_con0);
 128                 break;
 129         default:
 130                 printf("Unsupported PLL (%d)\n", pllreg);
 131                 return 0;
 132         }
 133
 134         fout = exynos_get_pll_clk(pllreg, r, k);
 135
 136         /* According to the user manual, in EVT1 MPLL and BPLL always gives
 137          * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
 138         if (pllreg == MPLL || pllreg == BPLL) {
 139                 pll_div2_sel = readl(&clk->pll_div2_sel);
 140
 141                 switch (pllreg) {
 142                 case MPLL:
 143                         fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
 144                                         & MPLL_FOUT_SEL_MASK;
 145                         break;
 146                 case BPLL:
 147                         fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
 148                                         & BPLL_FOUT_SEL_MASK;
 149                         break;
 150                 default:
 151                         fout_sel = -1;
 152                         break;
 153                 }
 154
 155                 if (fout_sel == 0)
 156                         fout /= 2;
 157         }
 158
 159         return fout;
 160 }
 161
 162 /* exynos4: return ARM clock frequency */
 163 static unsigned long exynos4_get_arm_clk(void)
 164 {
 165         struct exynos4_clock *clk =
 166                 (struct exynos4_clock *)samsung_get_base_clock();
 167         unsigned long div;
 168         unsigned long armclk;
 169         unsigned int core_ratio;
 170         unsigned int core2_ratio;
 171
 172         div = readl(&clk->div_cpu0);
 173
 174         /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
 175         core_ratio = (div >> 0) & 0x7;
 176         core2_ratio = (div >> 28) & 0x7;
 177
 178         armclk = get_pll_clk(APLL) / (core_ratio + 1);
 179         armclk /= (core2_ratio + 1);
 180
 181         return armclk;
 182 }
 183
 184 /* exynos5: return ARM clock frequency */
 185 static unsigned long exynos5_get_arm_clk(void)
 186 {
 187         struct exynos5_clock *clk =
 188                 (struct exynos5_clock *)samsung_get_base_clock();
 189         unsigned long div;
 190         unsigned long armclk;
 191         unsigned int arm_ratio;
 192         unsigned int arm2_ratio;
 193
 194         div = readl(&clk->div_cpu0);
 195
 196         /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
 197         arm_ratio = (div >> 0) & 0x7;
 198         arm2_ratio = (div >> 28) & 0x7;
 199
 200         armclk = get_pll_clk(APLL) / (arm_ratio + 1);
 201         armclk /= (arm2_ratio + 1);
 202
 203         return armclk;
 204 }
 205
 206 /* exynos4: return pwm clock frequency */
 207 static unsigned long exynos4_get_pwm_clk(void)
 208 {
 209         struct exynos4_clock *clk =
 210                 (struct exynos4_clock *)samsung_get_base_clock();
 211         unsigned long pclk, sclk;
 212         unsigned int sel;
 213         unsigned int ratio;
 214
 215         if (s5p_get_cpu_rev() == 0) {
 216                 /*
 217                  * CLK_SRC_PERIL0
 218                  * PWM_SEL [27:24]
 219                  */
 220                 sel = readl(&clk->src_peril0);
 221                 sel = (sel >> 24) & 0xf;
 222
 223                 if (sel == 0x6)
 224                         sclk = get_pll_clk(MPLL);
 225                 else if (sel == 0x7)
 226                         sclk = get_pll_clk(EPLL);
 227                 else if (sel == 0x8)
 228                         sclk = get_pll_clk(VPLL);
 229                 else
 230                         return 0;
 231
 232                 /*
 233                  * CLK_DIV_PERIL3
 234                  * PWM_RATIO [3:0]
 235                  */
 236                 ratio = readl(&clk->div_peril3);
 237                 ratio = ratio & 0xf;
 238         } else if (s5p_get_cpu_rev() == 1) {
 239                 sclk = get_pll_clk(MPLL);
 240                 ratio = 8;
 241         } else
 242                 return 0;
 243
 244         pclk = sclk / (ratio + 1);
 245
 246         return pclk;
 247 }
 248
 249 /* exynos5: return pwm clock frequency */
 250 static unsigned long exynos5_get_pwm_clk(void)
 251 {
 252         struct exynos5_clock *clk =
 253                 (struct exynos5_clock *)samsung_get_base_clock();
 254         unsigned long pclk, sclk;
 255         unsigned int ratio;
 256
 257         /*
 258          * CLK_DIV_PERIC3
 259          * PWM_RATIO [3:0]
 260          */
 261         ratio = readl(&clk->div_peric3);
 262         ratio = ratio & 0xf;
 263         sclk = get_pll_clk(MPLL);
 264
 265         pclk = sclk / (ratio + 1);
 266
 267         return pclk;
 268 }
 269
 270 /* exynos4: return uart clock frequency */
 271 static unsigned long exynos4_get_uart_clk(int dev_index)
 272 {
 273         struct exynos4_clock *clk =
 274                 (struct exynos4_clock *)samsung_get_base_clock();
 275         unsigned long uclk, sclk;
 276         unsigned int sel;
 277         unsigned int ratio;
 278
 279         /*
 280          * CLK_SRC_PERIL0
 281          * UART0_SEL [3:0]
 282          * UART1_SEL [7:4]
 283          * UART2_SEL [8:11]
 284          * UART3_SEL [12:15]
 285          * UART4_SEL [16:19]
 286          * UART5_SEL [23:20]
 287          */
 288         sel = readl(&clk->src_peril0);
 289         sel = (sel >> (dev_index << 2)) & 0xf;
 290
 291         if (sel == 0x6)
 292                 sclk = get_pll_clk(MPLL);
 293         else if (sel == 0x7)
 294                 sclk = get_pll_clk(EPLL);
 295         else if (sel == 0x8)
 296                 sclk = get_pll_clk(VPLL);
 297         else
 298                 return 0;
 299
 300         /*
 301          * CLK_DIV_PERIL0
 302          * UART0_RATIO [3:0]
 303          * UART1_RATIO [7:4]
 304          * UART2_RATIO [8:11]
 305          * UART3_RATIO [12:15]
 306          * UART4_RATIO [16:19]
 307          * UART5_RATIO [23:20]
 308          */
 309         ratio = readl(&clk->div_peril0);
 310         ratio = (ratio >> (dev_index << 2)) & 0xf;
 311
 312         uclk = sclk / (ratio + 1);
 313
 314         return uclk;
 315 }
 316
 317 /* exynos5: return uart clock frequency */
 318 static unsigned long exynos5_get_uart_clk(int dev_index)
 319 {
 320         struct exynos5_clock *clk =
 321                 (struct exynos5_clock *)samsung_get_base_clock();
 322         unsigned long uclk, sclk;
 323         unsigned int sel;
 324         unsigned int ratio;
 325
 326         /*
 327          * CLK_SRC_PERIC0
 328          * UART0_SEL [3:0]
 329          * UART1_SEL [7:4]
 330          * UART2_SEL [8:11]
 331          * UART3_SEL [12:15]
 332          * UART4_SEL [16:19]
 333          * UART5_SEL [23:20]
 334          */
 335         sel = readl(&clk->src_peric0);
 336         sel = (sel >> (dev_index << 2)) & 0xf;
 337
 338         if (sel == 0x6)
 339                 sclk = get_pll_clk(MPLL);
 340         else if (sel == 0x7)
 341                 sclk = get_pll_clk(EPLL);
 342         else if (sel == 0x8)
 343                 sclk = get_pll_clk(VPLL);
 344         else
 345                 return 0;
 346
 347         /*
 348          * CLK_DIV_PERIC0
 349          * UART0_RATIO [3:0]
 350          * UART1_RATIO [7:4]
 351          * UART2_RATIO [8:11]
 352          * UART3_RATIO [12:15]
 353          * UART4_RATIO [16:19]
 354          * UART5_RATIO [23:20]
 355          */
 356         ratio = readl(&clk->div_peric0);
 357         ratio = (ratio >> (dev_index << 2)) & 0xf;
 358
 359         uclk = sclk / (ratio + 1);
 360
 361         return uclk;
 362 }
 363
 364 /* exynos4: set the mmc clock */
 365 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 366 {
 367         struct exynos4_clock *clk =
 368                 (struct exynos4_clock *)samsung_get_base_clock();
 369         unsigned int addr;
 370         unsigned int val;
 371
 372         /*
 373          * CLK_DIV_FSYS1
 374          * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
 375          * CLK_DIV_FSYS2
 376          * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
 377          */
 378         if (dev_index < 2) {
 379                 addr = (unsigned int)&clk->div_fsys1;
 380         } else {
 381                 addr = (unsigned int)&clk->div_fsys2;
 382                 dev_index -= 2;
 383         }
 384
 385         val = readl(addr);
 386         val &= ~(0xff << ((dev_index << 4) + 8));
 387         val |= (div & 0xff) << ((dev_index << 4) + 8);
 388         writel(val, addr);
 389 }
 390
 391 /* exynos5: set the mmc clock */
 392 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 393 {
 394         struct exynos5_clock *clk =
 395                 (struct exynos5_clock *)samsung_get_base_clock();
 396         unsigned int addr;
 397         unsigned int val;
 398
 399         /*
 400          * CLK_DIV_FSYS1
 401          * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
 402          * CLK_DIV_FSYS2
 403          * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
 404          */
 405         if (dev_index < 2) {
 406                 addr = (unsigned int)&clk->div_fsys1;
 407         } else {
 408                 addr = (unsigned int)&clk->div_fsys2;
 409                 dev_index -= 2;
 410         }
 411
 412         val = readl(addr);
 413         val &= ~(0xff << ((dev_index << 4) + 8));
 414         val |= (div & 0xff) << ((dev_index << 4) + 8);
 415         writel(val, addr);
 416 }
 417
 418 /* get_lcd_clk: return lcd clock frequency */
 419 static unsigned long exynos4_get_lcd_clk(void)
 420 {
 421         struct exynos4_clock *clk =
 422                 (struct exynos4_clock *)samsung_get_base_clock();
 423         unsigned long pclk, sclk;
 424         unsigned int sel;
 425         unsigned int ratio;
 426
 427         /*
 428          * CLK_SRC_LCD0
 429          * FIMD0_SEL [3:0]
 430          */
 431         sel = readl(&clk->src_lcd0);
 432         sel = sel & 0xf;
 433
 434         /*
 435          * 0x6: SCLK_MPLL
 436          * 0x7: SCLK_EPLL
 437          * 0x8: SCLK_VPLL
 438          */
 439         if (sel == 0x6)
 440                 sclk = get_pll_clk(MPLL);
 441         else if (sel == 0x7)
 442                 sclk = get_pll_clk(EPLL);
 443         else if (sel == 0x8)
 444                 sclk = get_pll_clk(VPLL);
 445         else
 446                 return 0;
 447
 448         /*
 449          * CLK_DIV_LCD0
 450          * FIMD0_RATIO [3:0]
 451          */
 452         ratio = readl(&clk->div_lcd0);
 453         ratio = ratio & 0xf;
 454
 455         pclk = sclk / (ratio + 1);
 456
 457         return pclk;
 458 }
 459
 460 /* get_lcd_clk: return lcd clock frequency */
 461 static unsigned long exynos5_get_lcd_clk(void)
 462 {
 463         struct exynos5_clock *clk =
 464                 (struct exynos5_clock *)samsung_get_base_clock();
 465         unsigned long pclk, sclk;
 466         unsigned int sel;
 467         unsigned int ratio;
 468
 469         /*
 470          * CLK_SRC_LCD0
 471          * FIMD0_SEL [3:0]
 472          */
 473         sel = readl(&clk->src_disp1_0);
 474         sel = sel & 0xf;
 475
 476         /*
 477          * 0x6: SCLK_MPLL
 478          * 0x7: SCLK_EPLL
 479          * 0x8: SCLK_VPLL
 480          */
 481         if (sel == 0x6)
 482                 sclk = get_pll_clk(MPLL);
 483         else if (sel == 0x7)
 484                 sclk = get_pll_clk(EPLL);
 485         else if (sel == 0x8)
 486                 sclk = get_pll_clk(VPLL);
 487         else
 488                 return 0;
 489
 490         /*
 491          * CLK_DIV_LCD0
 492          * FIMD0_RATIO [3:0]
 493          */
 494         ratio = readl(&clk->div_disp1_0);
 495         ratio = ratio & 0xf;
 496
 497         pclk = sclk / (ratio + 1);
 498
 499         return pclk;
 500 }
 501
 502 void exynos4_set_lcd_clk(void)
 503 {
 504         struct exynos4_clock *clk =
 505             (struct exynos4_clock *)samsung_get_base_clock();
 506         unsigned int cfg = 0;
 507
 508         /*
 509          * CLK_GATE_BLOCK
 510          * CLK_CAM      [0]
 511          * CLK_TV       [1]
 512          * CLK_MFC      [2]
 513          * CLK_G3D      [3]
 514          * CLK_LCD0     [4]
 515          * CLK_LCD1     [5]
 516          * CLK_GPS      [7]
 517          */
 518         cfg = readl(&clk->gate_block);
 519         cfg |= 1 << 4;
 520         writel(cfg, &clk->gate_block);
 521
 522         /*
 523          * CLK_SRC_LCD0
 524          * FIMD0_SEL            [3:0]
 525          * MDNIE0_SEL           [7:4]
 526          * MDNIE_PWM0_SEL       [8:11]
 527          * MIPI0_SEL            [12:15]
 528          * set lcd0 src clock 0x6: SCLK_MPLL
 529          */
 530         cfg = readl(&clk->src_lcd0);
 531         cfg &= ~(0xf);
 532         cfg |= 0x6;
 533         writel(cfg, &clk->src_lcd0);
 534
 535         /*
 536          * CLK_GATE_IP_LCD0
 537          * CLK_FIMD0            [0]
 538          * CLK_MIE0             [1]
 539          * CLK_MDNIE0           [2]
 540          * CLK_DSIM0            [3]
 541          * CLK_SMMUFIMD0        [4]
 542          * CLK_PPMULCD0         [5]
 543          * Gating all clocks for FIMD0
 544          */
 545         cfg = readl(&clk->gate_ip_lcd0);
 546         cfg |= 1 << 0;
 547         writel(cfg, &clk->gate_ip_lcd0);
 548
 549         /*
 550          * CLK_DIV_LCD0
 551          * FIMD0_RATIO          [3:0]
 552          * MDNIE0_RATIO         [7:4]
 553          * MDNIE_PWM0_RATIO     [11:8]
 554          * MDNIE_PWM_PRE_RATIO  [15:12]
 555          * MIPI0_RATIO          [19:16]
 556          * MIPI0_PRE_RATIO      [23:20]
 557          * set fimd ratio
 558          */
 559         cfg &= ~(0xf);
 560         cfg |= 0x1;
 561         writel(cfg, &clk->div_lcd0);
 562 }
 563
 564 void exynos5_set_lcd_clk(void)
 565 {
 566         struct exynos5_clock *clk =
 567             (struct exynos5_clock *)samsung_get_base_clock();
 568         unsigned int cfg = 0;
 569
 570         /*
 571          * CLK_GATE_BLOCK
 572          * CLK_CAM      [0]
 573          * CLK_TV       [1]
 574          * CLK_MFC      [2]
 575          * CLK_G3D      [3]
 576          * CLK_LCD0     [4]
 577          * CLK_LCD1     [5]
 578          * CLK_GPS      [7]
 579          */
 580         cfg = readl(&clk->gate_block);
 581         cfg |= 1 << 4;
 582         writel(cfg, &clk->gate_block);
 583
 584         /*
 585          * CLK_SRC_LCD0
 586          * FIMD0_SEL            [3:0]
 587          * MDNIE0_SEL           [7:4]
 588          * MDNIE_PWM0_SEL       [8:11]
 589          * MIPI0_SEL            [12:15]
 590          * set lcd0 src clock 0x6: SCLK_MPLL
 591          */
 592         cfg = readl(&clk->src_disp1_0);
 593         cfg &= ~(0xf);
 594         cfg |= 0x8;
 595         writel(cfg, &clk->src_disp1_0);
 596
 597         /*
 598          * CLK_GATE_IP_LCD0
 599          * CLK_FIMD0            [0]
 600          * CLK_MIE0             [1]
 601          * CLK_MDNIE0           [2]
 602          * CLK_DSIM0            [3]
 603          * CLK_SMMUFIMD0        [4]
 604          * CLK_PPMULCD0         [5]
 605          * Gating all clocks for FIMD0
 606          */
 607         cfg = readl(&clk->gate_ip_disp1);
 608         cfg |= 1 << 0;
 609         writel(cfg, &clk->gate_ip_disp1);
 610
 611         /*
 612          * CLK_DIV_LCD0
 613          * FIMD0_RATIO          [3:0]
 614          * MDNIE0_RATIO         [7:4]
 615          * MDNIE_PWM0_RATIO     [11:8]
 616          * MDNIE_PWM_PRE_RATIO  [15:12]
 617          * MIPI0_RATIO          [19:16]
 618          * MIPI0_PRE_RATIO      [23:20]
 619          * set fimd ratio
 620          */
 621         cfg &= ~(0xf);
 622         cfg |= 0x0;
 623         writel(cfg, &clk->div_disp1_0);
 624 }
 625
 626 void exynos4_set_mipi_clk(void)
 627 {
 628         struct exynos4_clock *clk =
 629             (struct exynos4_clock *)samsung_get_base_clock();
 630         unsigned int cfg = 0;
 631
 632         /*
 633          * CLK_SRC_LCD0
 634          * FIMD0_SEL            [3:0]
 635          * MDNIE0_SEL           [7:4]
 636          * MDNIE_PWM0_SEL       [8:11]
 637          * MIPI0_SEL            [12:15]
 638          * set mipi0 src clock 0x6: SCLK_MPLL
 639          */
 640         cfg = readl(&clk->src_lcd0);
 641         cfg &= ~(0xf << 12);
 642         cfg |= (0x6 << 12);
 643         writel(cfg, &clk->src_lcd0);
 644
 645         /*
 646          * CLK_SRC_MASK_LCD0
 647          * FIMD0_MASK           [0]
 648          * MDNIE0_MASK          [4]
 649          * MDNIE_PWM0_MASK      [8]
 650          * MIPI0_MASK           [12]
 651          * set src mask mipi0 0x1: Unmask
 652          */
 653         cfg = readl(&clk->src_mask_lcd0);
 654         cfg |= (0x1 << 12);
 655         writel(cfg, &clk->src_mask_lcd0);
 656
 657         /*
 658          * CLK_GATE_IP_LCD0
 659          * CLK_FIMD0            [0]
 660          * CLK_MIE0             [1]
 661          * CLK_MDNIE0           [2]
 662          * CLK_DSIM0            [3]
 663          * CLK_SMMUFIMD0        [4]
 664          * CLK_PPMULCD0         [5]
 665          * Gating all clocks for MIPI0
 666          */
 667         cfg = readl(&clk->gate_ip_lcd0);
 668         cfg |= 1 << 3;
 669         writel(cfg, &clk->gate_ip_lcd0);
 670
 671         /*
 672          * CLK_DIV_LCD0
 673          * FIMD0_RATIO          [3:0]
 674          * MDNIE0_RATIO         [7:4]
 675          * MDNIE_PWM0_RATIO     [11:8]
 676          * MDNIE_PWM_PRE_RATIO  [15:12]
 677          * MIPI0_RATIO          [19:16]
 678          * MIPI0_PRE_RATIO      [23:20]
 679          * set mipi ratio
 680          */
 681         cfg &= ~(0xf << 16);
 682         cfg |= (0x1 << 16);
 683         writel(cfg, &clk->div_lcd0);
 684 }
 685
 686 /*
 687  * I2C
 688  *
 689  * exynos5: obtaining the I2C clock
 690  */
 691 static unsigned long exynos5_get_i2c_clk(void)
 692 {
 693         struct exynos5_clock *clk =
 694                 (struct exynos5_clock *)samsung_get_base_clock();
 695         unsigned long aclk_66, aclk_66_pre, sclk;
 696         unsigned int ratio;
 697
 698         sclk = get_pll_clk(MPLL);
 699
 700         ratio = (readl(&clk->div_top1)) >> 24;
 701         ratio &= 0x7;
 702         aclk_66_pre = sclk / (ratio + 1);
 703         ratio = readl(&clk->div_top0);
 704         ratio &= 0x7;
 705         aclk_66 = aclk_66_pre / (ratio + 1);
 706         return aclk_66;
 707 }
 708
 709 unsigned long get_pll_clk(int pllreg)
 710 {
 711         if (cpu_is_exynos5())
 712                 return exynos5_get_pll_clk(pllreg);
 713         else
 714                 return exynos4_get_pll_clk(pllreg);
 715 }
 716
 717 unsigned long get_arm_clk(void)
 718 {
 719         if (cpu_is_exynos5())
 720                 return exynos5_get_arm_clk();
 721         else
 722                 return exynos4_get_arm_clk();
 723 }
 724
 725 unsigned long get_i2c_clk(void)
 726 {
 727         if (cpu_is_exynos5()) {
 728                 return exynos5_get_i2c_clk();
 729         } else {
 730                 debug("I2C clock is not set for this CPU\n");
 731                 return 0;
 732         }
 733 }
 734
 735 unsigned long get_pwm_clk(void)
 736 {
 737         if (cpu_is_exynos5())
 738                 return exynos5_get_pwm_clk();
 739         else
 740                 return exynos4_get_pwm_clk();
 741 }
 742
 743 unsigned long get_uart_clk(int dev_index)
 744 {
 745         if (cpu_is_exynos5())
 746                 return exynos5_get_uart_clk(dev_index);
 747         else
 748                 return exynos4_get_uart_clk(dev_index);
 749 }
 750
 751 void set_mmc_clk(int dev_index, unsigned int div)
 752 {
 753         if (cpu_is_exynos5())
 754                 exynos5_set_mmc_clk(dev_index, div);
 755         else
 756                 exynos4_set_mmc_clk(dev_index, div);
 757 }
 758
 759 unsigned long get_lcd_clk(void)
 760 {
 761         if (cpu_is_exynos4())
 762                 return exynos4_get_lcd_clk();
 763         else
 764                 return exynos5_get_lcd_clk();
 765 }
 766
 767 void set_lcd_clk(void)
 768 {
 769         if (cpu_is_exynos4())
 770                 exynos4_set_lcd_clk();
 771         else
 772                 exynos5_set_lcd_clk();
 773 }
 774
 775 void set_mipi_clk(void)
 776 {
 777         if (cpu_is_exynos4())
 778                 exynos4_set_mipi_clk();
 779 }