2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/periph.h>
14 #define PLL_DIV_1024 1024
15 #define PLL_DIV_65535 65535
16 #define PLL_DIV_65536 65536
19 * This structure is to store the src bit, div bit and prediv bit
20 * positions of the peripheral clocks of the src and div registers
28 /* src_bit div_bit prediv_bit */
29 static struct clk_bit_info clk_bit_info[] = {
61 /* Epll Clock division values to achive different frequency output */
62 static struct set_epll_con_val exynos5_epll_div[] = {
63 { 192000000, 0, 48, 3, 1, 0 },
64 { 180000000, 0, 45, 3, 1, 0 },
65 { 73728000, 1, 73, 3, 3, 47710 },
66 { 67737600, 1, 90, 4, 3, 20762 },
67 { 49152000, 0, 49, 3, 3, 9961 },
68 { 45158400, 0, 45, 3, 3, 10381 },
69 { 180633600, 0, 45, 3, 1, 10381 }
72 /* exynos: return pll clock frequency */
73 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
75 unsigned long m, p, s = 0, mask, fout;
79 * APLL_CON: MIDV [25:16]
80 * MPLL_CON: MIDV [25:16]
81 * EPLL_CON: MIDV [24:16]
82 * VPLL_CON: MIDV [24:16]
83 * BPLL_CON: MIDV [25:16]: Exynos5
85 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
97 freq = CONFIG_SYS_CLK_FREQ;
99 if (pllreg == EPLL || pllreg == RPLL) {
101 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
102 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
103 } else if (pllreg == VPLL) {
108 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
111 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
114 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
116 if (proid_is_exynos4210())
118 else if (proid_is_exynos4412())
120 else if (proid_is_exynos5250() || proid_is_exynos5420())
125 fout = (m + k / div) * (freq / (p * (1 << s)));
128 * Exynos4412 / Exynos5250
129 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
132 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
134 if (proid_is_exynos4210())
135 fout = m * (freq / (p * (1 << (s - 1))));
137 fout = m * (freq / (p * (1 << s)));
142 /* exynos4: return pll clock frequency */
143 static unsigned long exynos4_get_pll_clk(int pllreg)
145 struct exynos4_clock *clk =
146 (struct exynos4_clock *)samsung_get_base_clock();
147 unsigned long r, k = 0;
151 r = readl(&clk->apll_con0);
154 r = readl(&clk->mpll_con0);
157 r = readl(&clk->epll_con0);
158 k = readl(&clk->epll_con1);
161 r = readl(&clk->vpll_con0);
162 k = readl(&clk->vpll_con1);
165 printf("Unsupported PLL (%d)\n", pllreg);
169 return exynos_get_pll_clk(pllreg, r, k);
172 /* exynos4x12: return pll clock frequency */
173 static unsigned long exynos4x12_get_pll_clk(int pllreg)
175 struct exynos4x12_clock *clk =
176 (struct exynos4x12_clock *)samsung_get_base_clock();
177 unsigned long r, k = 0;
181 r = readl(&clk->apll_con0);
184 r = readl(&clk->mpll_con0);
187 r = readl(&clk->epll_con0);
188 k = readl(&clk->epll_con1);
191 r = readl(&clk->vpll_con0);
192 k = readl(&clk->vpll_con1);
195 printf("Unsupported PLL (%d)\n", pllreg);
199 return exynos_get_pll_clk(pllreg, r, k);
202 /* exynos5: return pll clock frequency */
203 static unsigned long exynos5_get_pll_clk(int pllreg)
205 struct exynos5_clock *clk =
206 (struct exynos5_clock *)samsung_get_base_clock();
207 unsigned long r, k = 0, fout;
208 unsigned int pll_div2_sel, fout_sel;
212 r = readl(&clk->apll_con0);
215 r = readl(&clk->mpll_con0);
218 r = readl(&clk->epll_con0);
219 k = readl(&clk->epll_con1);
222 r = readl(&clk->vpll_con0);
223 k = readl(&clk->vpll_con1);
226 r = readl(&clk->bpll_con0);
229 printf("Unsupported PLL (%d)\n", pllreg);
233 fout = exynos_get_pll_clk(pllreg, r, k);
235 /* According to the user manual, in EVT1 MPLL and BPLL always gives
236 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
237 if (pllreg == MPLL || pllreg == BPLL) {
238 pll_div2_sel = readl(&clk->pll_div2_sel);
242 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
243 & MPLL_FOUT_SEL_MASK;
246 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
247 & BPLL_FOUT_SEL_MASK;
261 static unsigned long exynos5_get_periph_rate(int peripheral)
263 struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
264 unsigned long sclk, sub_clk;
265 unsigned int src, div, sub_div;
266 struct exynos5_clock *clk =
267 (struct exynos5_clock *)samsung_get_base_clock();
269 switch (peripheral) {
270 case PERIPH_ID_UART0:
271 case PERIPH_ID_UART1:
272 case PERIPH_ID_UART2:
273 case PERIPH_ID_UART3:
274 src = readl(&clk->src_peric0);
275 div = readl(&clk->div_peric0);
282 src = readl(&clk->src_peric0);
283 div = readl(&clk->div_peric3);
286 src = readl(&clk->src_mau);
287 div = readl(&clk->div_mau);
290 src = readl(&clk->src_peric1);
291 div = readl(&clk->div_peric1);
294 src = readl(&clk->src_peric1);
295 div = readl(&clk->div_peric2);
299 src = readl(&clk->sclk_src_isp);
300 div = readl(&clk->sclk_div_isp);
302 case PERIPH_ID_SDMMC0:
303 case PERIPH_ID_SDMMC1:
304 case PERIPH_ID_SDMMC2:
305 case PERIPH_ID_SDMMC3:
306 src = readl(&clk->src_fsys);
307 div = readl(&clk->div_fsys1);
317 sclk = exynos5_get_pll_clk(MPLL);
318 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
320 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
322 return (sclk / sub_div) / div;
324 debug("%s: invalid peripheral %d", __func__, peripheral);
328 src = (src >> bit_info->src_bit) & 0xf;
331 case EXYNOS_SRC_MPLL:
332 sclk = exynos5_get_pll_clk(MPLL);
334 case EXYNOS_SRC_EPLL:
335 sclk = exynos5_get_pll_clk(EPLL);
337 case EXYNOS_SRC_VPLL:
338 sclk = exynos5_get_pll_clk(VPLL);
344 /* Ratio clock division for this peripheral */
345 sub_div = (div >> bit_info->div_bit) & 0xf;
346 sub_clk = sclk / (sub_div + 1);
348 /* Pre-ratio clock division for SDMMC0 and 2 */
349 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
350 div = (div >> bit_info->prediv_bit) & 0xff;
351 return sub_clk / (div + 1);
357 unsigned long clock_get_periph_rate(int peripheral)
359 if (cpu_is_exynos5())
360 return exynos5_get_periph_rate(peripheral);
365 /* exynos5420: return pll clock frequency */
366 static unsigned long exynos5420_get_pll_clk(int pllreg)
368 struct exynos5420_clock *clk =
369 (struct exynos5420_clock *)samsung_get_base_clock();
370 unsigned long r, k = 0;
374 r = readl(&clk->apll_con0);
377 r = readl(&clk->mpll_con0);
380 r = readl(&clk->epll_con0);
381 k = readl(&clk->epll_con1);
384 r = readl(&clk->vpll_con0);
385 k = readl(&clk->vpll_con1);
388 r = readl(&clk->bpll_con0);
391 r = readl(&clk->rpll_con0);
392 k = readl(&clk->rpll_con1);
395 printf("Unsupported PLL (%d)\n", pllreg);
399 return exynos_get_pll_clk(pllreg, r, k);
402 /* exynos4: return ARM clock frequency */
403 static unsigned long exynos4_get_arm_clk(void)
405 struct exynos4_clock *clk =
406 (struct exynos4_clock *)samsung_get_base_clock();
408 unsigned long armclk;
409 unsigned int core_ratio;
410 unsigned int core2_ratio;
412 div = readl(&clk->div_cpu0);
414 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
415 core_ratio = (div >> 0) & 0x7;
416 core2_ratio = (div >> 28) & 0x7;
418 armclk = get_pll_clk(APLL) / (core_ratio + 1);
419 armclk /= (core2_ratio + 1);
424 /* exynos4x12: return ARM clock frequency */
425 static unsigned long exynos4x12_get_arm_clk(void)
427 struct exynos4x12_clock *clk =
428 (struct exynos4x12_clock *)samsung_get_base_clock();
430 unsigned long armclk;
431 unsigned int core_ratio;
432 unsigned int core2_ratio;
434 div = readl(&clk->div_cpu0);
436 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
437 core_ratio = (div >> 0) & 0x7;
438 core2_ratio = (div >> 28) & 0x7;
440 armclk = get_pll_clk(APLL) / (core_ratio + 1);
441 armclk /= (core2_ratio + 1);
446 /* exynos5: return ARM clock frequency */
447 static unsigned long exynos5_get_arm_clk(void)
449 struct exynos5_clock *clk =
450 (struct exynos5_clock *)samsung_get_base_clock();
452 unsigned long armclk;
453 unsigned int arm_ratio;
454 unsigned int arm2_ratio;
456 div = readl(&clk->div_cpu0);
458 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
459 arm_ratio = (div >> 0) & 0x7;
460 arm2_ratio = (div >> 28) & 0x7;
462 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
463 armclk /= (arm2_ratio + 1);
468 /* exynos4: return pwm clock frequency */
469 static unsigned long exynos4_get_pwm_clk(void)
471 struct exynos4_clock *clk =
472 (struct exynos4_clock *)samsung_get_base_clock();
473 unsigned long pclk, sclk;
477 if (s5p_get_cpu_rev() == 0) {
482 sel = readl(&clk->src_peril0);
483 sel = (sel >> 24) & 0xf;
486 sclk = get_pll_clk(MPLL);
488 sclk = get_pll_clk(EPLL);
490 sclk = get_pll_clk(VPLL);
498 ratio = readl(&clk->div_peril3);
500 } else if (s5p_get_cpu_rev() == 1) {
501 sclk = get_pll_clk(MPLL);
506 pclk = sclk / (ratio + 1);
511 /* exynos4x12: return pwm clock frequency */
512 static unsigned long exynos4x12_get_pwm_clk(void)
514 unsigned long pclk, sclk;
517 sclk = get_pll_clk(MPLL);
520 pclk = sclk / (ratio + 1);
525 /* exynos5420: return pwm clock frequency */
526 static unsigned long exynos5420_get_pwm_clk(void)
528 struct exynos5420_clock *clk =
529 (struct exynos5420_clock *)samsung_get_base_clock();
530 unsigned long pclk, sclk;
537 ratio = readl(&clk->div_peric0);
538 ratio = (ratio >> 28) & 0xf;
539 sclk = get_pll_clk(MPLL);
541 pclk = sclk / (ratio + 1);
546 /* exynos4: return uart clock frequency */
547 static unsigned long exynos4_get_uart_clk(int dev_index)
549 struct exynos4_clock *clk =
550 (struct exynos4_clock *)samsung_get_base_clock();
551 unsigned long uclk, sclk;
564 sel = readl(&clk->src_peril0);
565 sel = (sel >> (dev_index << 2)) & 0xf;
568 sclk = get_pll_clk(MPLL);
570 sclk = get_pll_clk(EPLL);
572 sclk = get_pll_clk(VPLL);
581 * UART3_RATIO [12:15]
582 * UART4_RATIO [16:19]
583 * UART5_RATIO [23:20]
585 ratio = readl(&clk->div_peril0);
586 ratio = (ratio >> (dev_index << 2)) & 0xf;
588 uclk = sclk / (ratio + 1);
593 /* exynos4x12: return uart clock frequency */
594 static unsigned long exynos4x12_get_uart_clk(int dev_index)
596 struct exynos4x12_clock *clk =
597 (struct exynos4x12_clock *)samsung_get_base_clock();
598 unsigned long uclk, sclk;
610 sel = readl(&clk->src_peril0);
611 sel = (sel >> (dev_index << 2)) & 0xf;
614 sclk = get_pll_clk(MPLL);
616 sclk = get_pll_clk(EPLL);
618 sclk = get_pll_clk(VPLL);
627 * UART3_RATIO [12:15]
628 * UART4_RATIO [16:19]
630 ratio = readl(&clk->div_peril0);
631 ratio = (ratio >> (dev_index << 2)) & 0xf;
633 uclk = sclk / (ratio + 1);
638 /* exynos5: return uart clock frequency */
639 static unsigned long exynos5_get_uart_clk(int dev_index)
641 struct exynos5_clock *clk =
642 (struct exynos5_clock *)samsung_get_base_clock();
643 unsigned long uclk, sclk;
656 sel = readl(&clk->src_peric0);
657 sel = (sel >> (dev_index << 2)) & 0xf;
660 sclk = get_pll_clk(MPLL);
662 sclk = get_pll_clk(EPLL);
664 sclk = get_pll_clk(VPLL);
673 * UART3_RATIO [12:15]
674 * UART4_RATIO [16:19]
675 * UART5_RATIO [23:20]
677 ratio = readl(&clk->div_peric0);
678 ratio = (ratio >> (dev_index << 2)) & 0xf;
680 uclk = sclk / (ratio + 1);
685 /* exynos5420: return uart clock frequency */
686 static unsigned long exynos5420_get_uart_clk(int dev_index)
688 struct exynos5420_clock *clk =
689 (struct exynos5420_clock *)samsung_get_base_clock();
690 unsigned long uclk, sclk;
700 * generalised calculation as follows
701 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
703 sel = readl(&clk->src_peric0);
704 sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
707 sclk = get_pll_clk(MPLL);
709 sclk = get_pll_clk(EPLL);
711 sclk = get_pll_clk(RPLL);
718 * UART1_RATIO [15:12]
719 * UART2_RATIO [19:16]
720 * UART3_RATIO [23:20]
721 * generalised calculation as follows
722 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
724 ratio = readl(&clk->div_peric0);
725 ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
727 uclk = sclk / (ratio + 1);
732 static unsigned long exynos4_get_mmc_clk(int dev_index)
734 struct exynos4_clock *clk =
735 (struct exynos4_clock *)samsung_get_base_clock();
736 unsigned long uclk, sclk;
737 unsigned int sel, ratio, pre_ratio;
740 sel = readl(&clk->src_fsys);
741 sel = (sel >> (dev_index << 2)) & 0xf;
744 sclk = get_pll_clk(MPLL);
746 sclk = get_pll_clk(EPLL);
748 sclk = get_pll_clk(VPLL);
755 ratio = readl(&clk->div_fsys1);
756 pre_ratio = readl(&clk->div_fsys1);
760 ratio = readl(&clk->div_fsys2);
761 pre_ratio = readl(&clk->div_fsys2);
764 ratio = readl(&clk->div_fsys3);
765 pre_ratio = readl(&clk->div_fsys3);
771 if (dev_index == 1 || dev_index == 3)
774 ratio = (ratio >> shift) & 0xf;
775 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
776 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
781 static unsigned long exynos5_get_mmc_clk(int dev_index)
783 struct exynos5_clock *clk =
784 (struct exynos5_clock *)samsung_get_base_clock();
785 unsigned long uclk, sclk;
786 unsigned int sel, ratio, pre_ratio;
789 sel = readl(&clk->src_fsys);
790 sel = (sel >> (dev_index << 2)) & 0xf;
793 sclk = get_pll_clk(MPLL);
795 sclk = get_pll_clk(EPLL);
797 sclk = get_pll_clk(VPLL);
804 ratio = readl(&clk->div_fsys1);
805 pre_ratio = readl(&clk->div_fsys1);
809 ratio = readl(&clk->div_fsys2);
810 pre_ratio = readl(&clk->div_fsys2);
816 if (dev_index == 1 || dev_index == 3)
819 ratio = (ratio >> shift) & 0xf;
820 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
821 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
826 static unsigned long exynos5420_get_mmc_clk(int dev_index)
828 struct exynos5420_clock *clk =
829 (struct exynos5420_clock *)samsung_get_base_clock();
830 unsigned long uclk, sclk;
831 unsigned int sel, ratio;
838 * generalised calculation as follows
839 * sel = (sel >> ((dev_index * 4) + 8)) & mask
841 sel = readl(&clk->src_fsys);
842 sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
845 sclk = get_pll_clk(MPLL);
847 sclk = get_pll_clk(EPLL);
856 * generalised calculation as follows
857 * ratio = (ratio >> (dev_index * 10)) & mask
859 ratio = readl(&clk->div_fsys1);
860 ratio = (ratio >> (dev_index * 10)) & 0x3ff;
862 uclk = (sclk / (ratio + 1));
867 /* exynos4: set the mmc clock */
868 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
870 struct exynos4_clock *clk =
871 (struct exynos4_clock *)samsung_get_base_clock();
877 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
879 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
881 * MMC4_PRE_RATIO [15:8]
884 addr = (unsigned int)&clk->div_fsys1;
885 } else if (dev_index == 4) {
886 addr = (unsigned int)&clk->div_fsys3;
889 addr = (unsigned int)&clk->div_fsys2;
894 val &= ~(0xff << ((dev_index << 4) + 8));
895 val |= (div & 0xff) << ((dev_index << 4) + 8);
899 /* exynos4x12: set the mmc clock */
900 static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
902 struct exynos4x12_clock *clk =
903 (struct exynos4x12_clock *)samsung_get_base_clock();
909 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
911 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
914 addr = (unsigned int)&clk->div_fsys1;
916 addr = (unsigned int)&clk->div_fsys2;
921 val &= ~(0xff << ((dev_index << 4) + 8));
922 val |= (div & 0xff) << ((dev_index << 4) + 8);
926 /* exynos5: set the mmc clock */
927 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
929 struct exynos5_clock *clk =
930 (struct exynos5_clock *)samsung_get_base_clock();
936 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
938 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
941 addr = (unsigned int)&clk->div_fsys1;
943 addr = (unsigned int)&clk->div_fsys2;
948 val &= ~(0xff << ((dev_index << 4) + 8));
949 val |= (div & 0xff) << ((dev_index << 4) + 8);
953 /* exynos5: set the mmc clock */
954 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
956 struct exynos5420_clock *clk =
957 (struct exynos5420_clock *)samsung_get_base_clock();
959 unsigned int val, shift;
967 addr = (unsigned int)&clk->div_fsys1;
968 shift = dev_index * 10;
971 val &= ~(0x3ff << shift);
972 val |= (div & 0x3ff) << shift;
976 /* get_lcd_clk: return lcd clock frequency */
977 static unsigned long exynos4_get_lcd_clk(void)
979 struct exynos4_clock *clk =
980 (struct exynos4_clock *)samsung_get_base_clock();
981 unsigned long pclk, sclk;
989 sel = readl(&clk->src_lcd0);
998 sclk = get_pll_clk(MPLL);
1000 sclk = get_pll_clk(EPLL);
1001 else if (sel == 0x8)
1002 sclk = get_pll_clk(VPLL);
1010 ratio = readl(&clk->div_lcd0);
1011 ratio = ratio & 0xf;
1013 pclk = sclk / (ratio + 1);
1018 /* get_lcd_clk: return lcd clock frequency */
1019 static unsigned long exynos5_get_lcd_clk(void)
1021 struct exynos5_clock *clk =
1022 (struct exynos5_clock *)samsung_get_base_clock();
1023 unsigned long pclk, sclk;
1031 sel = readl(&clk->src_disp1_0);
1040 sclk = get_pll_clk(MPLL);
1041 else if (sel == 0x7)
1042 sclk = get_pll_clk(EPLL);
1043 else if (sel == 0x8)
1044 sclk = get_pll_clk(VPLL);
1052 ratio = readl(&clk->div_disp1_0);
1053 ratio = ratio & 0xf;
1055 pclk = sclk / (ratio + 1);
1060 void exynos4_set_lcd_clk(void)
1062 struct exynos4_clock *clk =
1063 (struct exynos4_clock *)samsung_get_base_clock();
1064 unsigned int cfg = 0;
1076 cfg = readl(&clk->gate_block);
1078 writel(cfg, &clk->gate_block);
1084 * MDNIE_PWM0_SEL [8:11]
1086 * set lcd0 src clock 0x6: SCLK_MPLL
1088 cfg = readl(&clk->src_lcd0);
1091 writel(cfg, &clk->src_lcd0);
1101 * Gating all clocks for FIMD0
1103 cfg = readl(&clk->gate_ip_lcd0);
1105 writel(cfg, &clk->gate_ip_lcd0);
1110 * MDNIE0_RATIO [7:4]
1111 * MDNIE_PWM0_RATIO [11:8]
1112 * MDNIE_PWM_PRE_RATIO [15:12]
1113 * MIPI0_RATIO [19:16]
1114 * MIPI0_PRE_RATIO [23:20]
1117 cfg = readl(&clk->div_lcd0);
1120 writel(cfg, &clk->div_lcd0);
1123 void exynos5_set_lcd_clk(void)
1125 struct exynos5_clock *clk =
1126 (struct exynos5_clock *)samsung_get_base_clock();
1127 unsigned int cfg = 0;
1139 cfg = readl(&clk->gate_block);
1141 writel(cfg, &clk->gate_block);
1147 * MDNIE_PWM0_SEL [8:11]
1149 * set lcd0 src clock 0x6: SCLK_MPLL
1151 cfg = readl(&clk->src_disp1_0);
1154 writel(cfg, &clk->src_disp1_0);
1164 * Gating all clocks for FIMD0
1166 cfg = readl(&clk->gate_ip_disp1);
1168 writel(cfg, &clk->gate_ip_disp1);
1173 * MDNIE0_RATIO [7:4]
1174 * MDNIE_PWM0_RATIO [11:8]
1175 * MDNIE_PWM_PRE_RATIO [15:12]
1176 * MIPI0_RATIO [19:16]
1177 * MIPI0_PRE_RATIO [23:20]
1180 cfg = readl(&clk->div_disp1_0);
1183 writel(cfg, &clk->div_disp1_0);
1186 void exynos4_set_mipi_clk(void)
1188 struct exynos4_clock *clk =
1189 (struct exynos4_clock *)samsung_get_base_clock();
1190 unsigned int cfg = 0;
1196 * MDNIE_PWM0_SEL [8:11]
1198 * set mipi0 src clock 0x6: SCLK_MPLL
1200 cfg = readl(&clk->src_lcd0);
1201 cfg &= ~(0xf << 12);
1203 writel(cfg, &clk->src_lcd0);
1209 * MDNIE_PWM0_MASK [8]
1211 * set src mask mipi0 0x1: Unmask
1213 cfg = readl(&clk->src_mask_lcd0);
1215 writel(cfg, &clk->src_mask_lcd0);
1225 * Gating all clocks for MIPI0
1227 cfg = readl(&clk->gate_ip_lcd0);
1229 writel(cfg, &clk->gate_ip_lcd0);
1234 * MDNIE0_RATIO [7:4]
1235 * MDNIE_PWM0_RATIO [11:8]
1236 * MDNIE_PWM_PRE_RATIO [15:12]
1237 * MIPI0_RATIO [19:16]
1238 * MIPI0_PRE_RATIO [23:20]
1241 cfg = readl(&clk->div_lcd0);
1242 cfg &= ~(0xf << 16);
1244 writel(cfg, &clk->div_lcd0);
1250 * exynos5: obtaining the I2C clock
1252 static unsigned long exynos5_get_i2c_clk(void)
1254 struct exynos5_clock *clk =
1255 (struct exynos5_clock *)samsung_get_base_clock();
1256 unsigned long aclk_66, aclk_66_pre, sclk;
1259 sclk = get_pll_clk(MPLL);
1261 ratio = (readl(&clk->div_top1)) >> 24;
1263 aclk_66_pre = sclk / (ratio + 1);
1264 ratio = readl(&clk->div_top0);
1266 aclk_66 = aclk_66_pre / (ratio + 1);
1270 int exynos5_set_epll_clk(unsigned long rate)
1272 unsigned int epll_con, epll_con_k;
1274 unsigned int lockcnt;
1276 struct exynos5_clock *clk =
1277 (struct exynos5_clock *)samsung_get_base_clock();
1279 epll_con = readl(&clk->epll_con0);
1280 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1281 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1282 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1283 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1284 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1286 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1287 if (exynos5_epll_div[i].freq_out == rate)
1291 if (i == ARRAY_SIZE(exynos5_epll_div))
1294 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1295 epll_con |= exynos5_epll_div[i].en_lock_det <<
1296 EPLL_CON0_LOCK_DET_EN_SHIFT;
1297 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1298 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1299 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1302 * Required period ( in cycles) to genarate a stable clock output.
1303 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1304 * frequency input (as per spec)
1306 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1308 writel(lockcnt, &clk->epll_lock);
1309 writel(epll_con, &clk->epll_con0);
1310 writel(epll_con_k, &clk->epll_con1);
1312 start = get_timer(0);
1314 while (!(readl(&clk->epll_con0) &
1315 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1316 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1317 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1324 int exynos5_set_i2s_clk_source(unsigned int i2s_id)
1326 struct exynos5_clock *clk =
1327 (struct exynos5_clock *)samsung_get_base_clock();
1328 unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
1331 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
1332 clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
1333 (CLK_SRC_SCLK_EPLL));
1334 setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
1335 } else if (i2s_id == 1) {
1336 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1337 (CLK_SRC_SCLK_EPLL));
1344 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1345 unsigned int dst_frq,
1346 unsigned int i2s_id)
1348 struct exynos5_clock *clk =
1349 (struct exynos5_clock *)samsung_get_base_clock();
1352 if ((dst_frq == 0) || (src_frq == 0)) {
1353 debug("%s: Invalid requency input for prescaler\n", __func__);
1354 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1358 div = (src_frq / dst_frq);
1360 if (div > AUDIO_0_RATIO_MASK) {
1361 debug("%s: Frequency ratio is out of range\n",
1363 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1366 clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
1367 (div & AUDIO_0_RATIO_MASK));
1368 } else if(i2s_id == 1) {
1369 if (div > AUDIO_1_RATIO_MASK) {
1370 debug("%s: Frequency ratio is out of range\n",
1372 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1375 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1376 (div & AUDIO_1_RATIO_MASK));
1384 * Linearly searches for the most accurate main and fine stage clock scalars
1385 * (divisors) for a specified target frequency and scalar bit sizes by checking
1386 * all multiples of main_scalar_bits values. Will always return scalars up to or
1387 * slower than target.
1389 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1390 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1391 * @param input_freq Clock frequency to be scaled in Hz
1392 * @param target_freq Desired clock frequency in Hz
1393 * @param best_fine_scalar Pointer to store the fine stage divisor
1395 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1398 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1399 unsigned int fine_scalar_bits, unsigned int input_rate,
1400 unsigned int target_rate, unsigned int *best_fine_scalar)
1403 int best_main_scalar = -1;
1404 unsigned int best_error = target_rate;
1405 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1406 const unsigned int loops = 1 << main_scaler_bits;
1408 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1411 assert(best_fine_scalar != NULL);
1412 assert(main_scaler_bits <= fine_scalar_bits);
1414 *best_fine_scalar = 1;
1416 if (input_rate == 0 || target_rate == 0)
1419 if (target_rate >= input_rate)
1422 for (i = 1; i <= loops; i++) {
1423 const unsigned int effective_div = max(min(input_rate / i /
1424 target_rate, cap), 1);
1425 const unsigned int effective_rate = input_rate / i /
1427 const int error = target_rate - effective_rate;
1429 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1430 effective_rate, error);
1432 if (error >= 0 && error <= best_error) {
1434 best_main_scalar = i;
1435 *best_fine_scalar = effective_div;
1439 return best_main_scalar;
1442 static int exynos5_set_spi_clk(enum periph_id periph_id,
1445 struct exynos5_clock *clk =
1446 (struct exynos5_clock *)samsung_get_base_clock();
1449 unsigned shift, pre_shift;
1450 unsigned mask = 0xff;
1453 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1455 debug("%s: Cannot set clock rate for periph %d",
1456 __func__, periph_id);
1462 switch (periph_id) {
1463 case PERIPH_ID_SPI0:
1464 reg = &clk->div_peric1;
1468 case PERIPH_ID_SPI1:
1469 reg = &clk->div_peric1;
1473 case PERIPH_ID_SPI2:
1474 reg = &clk->div_peric2;
1478 case PERIPH_ID_SPI3:
1479 reg = &clk->sclk_div_isp;
1483 case PERIPH_ID_SPI4:
1484 reg = &clk->sclk_div_isp;
1489 debug("%s: Unsupported peripheral ID %d\n", __func__,
1493 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1494 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1499 static int exynos5420_set_spi_clk(enum periph_id periph_id,
1502 struct exynos5420_clock *clk =
1503 (struct exynos5420_clock *)samsung_get_base_clock();
1506 unsigned shift, pre_shift;
1507 unsigned div_mask = 0xf, pre_div_mask = 0xff;
1511 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1513 debug("%s: Cannot set clock rate for periph %d",
1514 __func__, periph_id);
1520 switch (periph_id) {
1521 case PERIPH_ID_SPI0:
1522 reg = &clk->div_peric1;
1524 pre_reg = &clk->div_peric4;
1527 case PERIPH_ID_SPI1:
1528 reg = &clk->div_peric1;
1530 pre_reg = &clk->div_peric4;
1533 case PERIPH_ID_SPI2:
1534 reg = &clk->div_peric1;
1536 pre_reg = &clk->div_peric4;
1539 case PERIPH_ID_SPI3:
1540 reg = &clk->div_isp1;
1542 pre_reg = &clk->div_isp1;
1545 case PERIPH_ID_SPI4:
1546 reg = &clk->div_isp1;
1548 pre_reg = &clk->div_isp1;
1552 debug("%s: Unsupported peripheral ID %d\n", __func__,
1557 clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
1558 clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
1559 (fine & pre_div_mask) << pre_shift);
1564 static unsigned long exynos4_get_i2c_clk(void)
1566 struct exynos4_clock *clk =
1567 (struct exynos4_clock *)samsung_get_base_clock();
1568 unsigned long sclk, aclk_100;
1571 sclk = get_pll_clk(APLL);
1573 ratio = (readl(&clk->div_top)) >> 4;
1575 aclk_100 = sclk / (ratio + 1);
1579 unsigned long get_pll_clk(int pllreg)
1581 if (cpu_is_exynos5()) {
1582 if (proid_is_exynos5420())
1583 return exynos5420_get_pll_clk(pllreg);
1584 return exynos5_get_pll_clk(pllreg);
1586 if (proid_is_exynos4412())
1587 return exynos4x12_get_pll_clk(pllreg);
1588 return exynos4_get_pll_clk(pllreg);
1592 unsigned long get_arm_clk(void)
1594 if (cpu_is_exynos5())
1595 return exynos5_get_arm_clk();
1597 if (proid_is_exynos4412())
1598 return exynos4x12_get_arm_clk();
1599 return exynos4_get_arm_clk();
1603 unsigned long get_i2c_clk(void)
1605 if (cpu_is_exynos5()) {
1606 return exynos5_get_i2c_clk();
1607 } else if (cpu_is_exynos4()) {
1608 return exynos4_get_i2c_clk();
1610 debug("I2C clock is not set for this CPU\n");
1615 unsigned long get_pwm_clk(void)
1617 if (cpu_is_exynos5()) {
1618 if (proid_is_exynos5420())
1619 return exynos5420_get_pwm_clk();
1620 return clock_get_periph_rate(PERIPH_ID_PWM0);
1622 if (proid_is_exynos4412())
1623 return exynos4x12_get_pwm_clk();
1624 return exynos4_get_pwm_clk();
1628 unsigned long get_uart_clk(int dev_index)
1630 if (cpu_is_exynos5()) {
1631 if (proid_is_exynos5420())
1632 return exynos5420_get_uart_clk(dev_index);
1633 return exynos5_get_uart_clk(dev_index);
1635 if (proid_is_exynos4412())
1636 return exynos4x12_get_uart_clk(dev_index);
1637 return exynos4_get_uart_clk(dev_index);
1641 unsigned long get_mmc_clk(int dev_index)
1643 if (cpu_is_exynos5()) {
1644 if (proid_is_exynos5420())
1645 return exynos5420_get_mmc_clk(dev_index);
1646 return exynos5_get_mmc_clk(dev_index);
1648 return exynos4_get_mmc_clk(dev_index);
1652 void set_mmc_clk(int dev_index, unsigned int div)
1654 if (cpu_is_exynos5()) {
1655 if (proid_is_exynos5420())
1656 exynos5420_set_mmc_clk(dev_index, div);
1658 exynos5_set_mmc_clk(dev_index, div);
1660 if (proid_is_exynos4412())
1661 exynos4x12_set_mmc_clk(dev_index, div);
1663 exynos4_set_mmc_clk(dev_index, div);
1667 unsigned long get_lcd_clk(void)
1669 if (cpu_is_exynos4())
1670 return exynos4_get_lcd_clk();
1672 return exynos5_get_lcd_clk();
1675 void set_lcd_clk(void)
1677 if (cpu_is_exynos4())
1678 exynos4_set_lcd_clk();
1680 exynos5_set_lcd_clk();
1683 void set_mipi_clk(void)
1685 if (cpu_is_exynos4())
1686 exynos4_set_mipi_clk();
1689 int set_spi_clk(int periph_id, unsigned int rate)
1691 if (cpu_is_exynos5()) {
1692 if (proid_is_exynos5420())
1693 return exynos5420_set_spi_clk(periph_id, rate);
1694 return exynos5_set_spi_clk(periph_id, rate);
1700 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
1701 unsigned int i2s_id)
1703 if (cpu_is_exynos5())
1704 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
1709 int set_i2s_clk_source(unsigned int i2s_id)
1711 if (cpu_is_exynos5())
1712 return exynos5_set_i2s_clk_source(i2s_id);
1717 int set_epll_clk(unsigned long rate)
1719 if (cpu_is_exynos5())
1720 return exynos5_set_epll_clk(rate);