2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/periph.h>
31 * This structure is to store the src bit, div bit and prediv bit
32 * positions of the peripheral clocks of the src and div registers
40 /* src_bit div_bit prediv_bit */
41 static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
73 /* Epll Clock division values to achive different frequency output */
74 static struct set_epll_con_val exynos5_epll_div[] = {
75 { 192000000, 0, 48, 3, 1, 0 },
76 { 180000000, 0, 45, 3, 1, 0 },
77 { 73728000, 1, 73, 3, 3, 47710 },
78 { 67737600, 1, 90, 4, 3, 20762 },
79 { 49152000, 0, 49, 3, 3, 9961 },
80 { 45158400, 0, 45, 3, 3, 10381 },
81 { 180633600, 0, 45, 3, 1, 10381 }
84 /* exynos: return pll clock frequency */
85 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
87 unsigned long m, p, s = 0, mask, fout;
90 * APLL_CON: MIDV [25:16]
91 * MPLL_CON: MIDV [25:16]
92 * EPLL_CON: MIDV [24:16]
93 * VPLL_CON: MIDV [24:16]
94 * BPLL_CON: MIDV [25:16]: Exynos5
96 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
101 m = (r >> 16) & mask;
108 freq = CONFIG_SYS_CLK_FREQ;
110 if (pllreg == EPLL) {
112 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
113 fout = (m + k / 65536) * (freq / (p * (1 << s)));
114 } else if (pllreg == VPLL) {
116 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
117 fout = (m + k / 1024) * (freq / (p * (1 << s)));
121 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
122 fout = m * (freq / (p * (1 << (s - 1))));
128 /* exynos4: return pll clock frequency */
129 static unsigned long exynos4_get_pll_clk(int pllreg)
131 struct exynos4_clock *clk =
132 (struct exynos4_clock *)samsung_get_base_clock();
133 unsigned long r, k = 0;
137 r = readl(&clk->apll_con0);
140 r = readl(&clk->mpll_con0);
143 r = readl(&clk->epll_con0);
144 k = readl(&clk->epll_con1);
147 r = readl(&clk->vpll_con0);
148 k = readl(&clk->vpll_con1);
151 printf("Unsupported PLL (%d)\n", pllreg);
155 return exynos_get_pll_clk(pllreg, r, k);
158 /* exynos4x12: return pll clock frequency */
159 static unsigned long exynos4x12_get_pll_clk(int pllreg)
161 struct exynos4x12_clock *clk =
162 (struct exynos4x12_clock *)samsung_get_base_clock();
163 unsigned long r, k = 0;
167 r = readl(&clk->apll_con0);
170 r = readl(&clk->mpll_con0);
173 r = readl(&clk->epll_con0);
174 k = readl(&clk->epll_con1);
177 r = readl(&clk->vpll_con0);
178 k = readl(&clk->vpll_con1);
181 printf("Unsupported PLL (%d)\n", pllreg);
185 return exynos_get_pll_clk(pllreg, r, k);
188 /* exynos5: return pll clock frequency */
189 static unsigned long exynos5_get_pll_clk(int pllreg)
191 struct exynos5_clock *clk =
192 (struct exynos5_clock *)samsung_get_base_clock();
193 unsigned long r, k = 0, fout;
194 unsigned int pll_div2_sel, fout_sel;
198 r = readl(&clk->apll_con0);
201 r = readl(&clk->mpll_con0);
204 r = readl(&clk->epll_con0);
205 k = readl(&clk->epll_con1);
208 r = readl(&clk->vpll_con0);
209 k = readl(&clk->vpll_con1);
212 r = readl(&clk->bpll_con0);
215 printf("Unsupported PLL (%d)\n", pllreg);
219 fout = exynos_get_pll_clk(pllreg, r, k);
221 /* According to the user manual, in EVT1 MPLL and BPLL always gives
222 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
223 if (pllreg == MPLL || pllreg == BPLL) {
224 pll_div2_sel = readl(&clk->pll_div2_sel);
228 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
229 & MPLL_FOUT_SEL_MASK;
232 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
233 & BPLL_FOUT_SEL_MASK;
247 static unsigned long exynos5_get_periph_rate(int peripheral)
249 struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
250 unsigned long sclk, sub_clk;
251 unsigned int src, div, sub_div;
252 struct exynos5_clock *clk =
253 (struct exynos5_clock *)samsung_get_base_clock();
255 switch (peripheral) {
256 case PERIPH_ID_UART0:
257 case PERIPH_ID_UART1:
258 case PERIPH_ID_UART2:
259 case PERIPH_ID_UART3:
260 src = readl(&clk->src_peric0);
261 div = readl(&clk->div_peric0);
268 src = readl(&clk->src_peric0);
269 div = readl(&clk->div_peric3);
273 src = readl(&clk->src_peric1);
274 div = readl(&clk->div_peric1);
277 src = readl(&clk->src_peric1);
278 div = readl(&clk->div_peric2);
282 src = readl(&clk->sclk_src_isp);
283 div = readl(&clk->sclk_div_isp);
285 case PERIPH_ID_SDMMC0:
286 case PERIPH_ID_SDMMC1:
287 case PERIPH_ID_SDMMC2:
288 case PERIPH_ID_SDMMC3:
289 src = readl(&clk->src_fsys);
290 div = readl(&clk->div_fsys1);
300 sclk = exynos5_get_pll_clk(MPLL);
301 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
303 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
305 return (sclk / sub_div) / div;
307 debug("%s: invalid peripheral %d", __func__, peripheral);
311 src = (src >> bit_info->src_bit) & 0xf;
314 case EXYNOS_SRC_MPLL:
315 sclk = exynos5_get_pll_clk(MPLL);
317 case EXYNOS_SRC_EPLL:
318 sclk = exynos5_get_pll_clk(EPLL);
320 case EXYNOS_SRC_VPLL:
321 sclk = exynos5_get_pll_clk(VPLL);
327 /* Ratio clock division for this peripheral */
328 sub_div = (div >> bit_info->div_bit) & 0xf;
329 sub_clk = sclk / (sub_div + 1);
331 /* Pre-ratio clock division for SDMMC0 and 2 */
332 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
333 div = (div >> bit_info->prediv_bit) & 0xff;
334 return sub_clk / (div + 1);
340 unsigned long clock_get_periph_rate(int peripheral)
342 if (cpu_is_exynos5())
343 return exynos5_get_periph_rate(peripheral);
348 /* exynos4: return ARM clock frequency */
349 static unsigned long exynos4_get_arm_clk(void)
351 struct exynos4_clock *clk =
352 (struct exynos4_clock *)samsung_get_base_clock();
354 unsigned long armclk;
355 unsigned int core_ratio;
356 unsigned int core2_ratio;
358 div = readl(&clk->div_cpu0);
360 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
361 core_ratio = (div >> 0) & 0x7;
362 core2_ratio = (div >> 28) & 0x7;
364 armclk = get_pll_clk(APLL) / (core_ratio + 1);
365 armclk /= (core2_ratio + 1);
370 /* exynos4x12: return ARM clock frequency */
371 static unsigned long exynos4x12_get_arm_clk(void)
373 struct exynos4x12_clock *clk =
374 (struct exynos4x12_clock *)samsung_get_base_clock();
376 unsigned long armclk;
377 unsigned int core_ratio;
378 unsigned int core2_ratio;
380 div = readl(&clk->div_cpu0);
382 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
383 core_ratio = (div >> 0) & 0x7;
384 core2_ratio = (div >> 28) & 0x7;
386 armclk = get_pll_clk(APLL) / (core_ratio + 1);
387 armclk /= (core2_ratio + 1);
392 /* exynos5: return ARM clock frequency */
393 static unsigned long exynos5_get_arm_clk(void)
395 struct exynos5_clock *clk =
396 (struct exynos5_clock *)samsung_get_base_clock();
398 unsigned long armclk;
399 unsigned int arm_ratio;
400 unsigned int arm2_ratio;
402 div = readl(&clk->div_cpu0);
404 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
405 arm_ratio = (div >> 0) & 0x7;
406 arm2_ratio = (div >> 28) & 0x7;
408 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
409 armclk /= (arm2_ratio + 1);
414 /* exynos4: return pwm clock frequency */
415 static unsigned long exynos4_get_pwm_clk(void)
417 struct exynos4_clock *clk =
418 (struct exynos4_clock *)samsung_get_base_clock();
419 unsigned long pclk, sclk;
423 if (s5p_get_cpu_rev() == 0) {
428 sel = readl(&clk->src_peril0);
429 sel = (sel >> 24) & 0xf;
432 sclk = get_pll_clk(MPLL);
434 sclk = get_pll_clk(EPLL);
436 sclk = get_pll_clk(VPLL);
444 ratio = readl(&clk->div_peril3);
446 } else if (s5p_get_cpu_rev() == 1) {
447 sclk = get_pll_clk(MPLL);
452 pclk = sclk / (ratio + 1);
457 /* exynos4x12: return pwm clock frequency */
458 static unsigned long exynos4x12_get_pwm_clk(void)
460 unsigned long pclk, sclk;
463 sclk = get_pll_clk(MPLL);
466 pclk = sclk / (ratio + 1);
471 /* exynos5: return pwm clock frequency */
472 static unsigned long exynos5_get_pwm_clk(void)
474 struct exynos5_clock *clk =
475 (struct exynos5_clock *)samsung_get_base_clock();
476 unsigned long pclk, sclk;
483 ratio = readl(&clk->div_peric3);
485 sclk = get_pll_clk(MPLL);
487 pclk = sclk / (ratio + 1);
492 /* exynos4: return uart clock frequency */
493 static unsigned long exynos4_get_uart_clk(int dev_index)
495 struct exynos4_clock *clk =
496 (struct exynos4_clock *)samsung_get_base_clock();
497 unsigned long uclk, sclk;
510 sel = readl(&clk->src_peril0);
511 sel = (sel >> (dev_index << 2)) & 0xf;
514 sclk = get_pll_clk(MPLL);
516 sclk = get_pll_clk(EPLL);
518 sclk = get_pll_clk(VPLL);
527 * UART3_RATIO [12:15]
528 * UART4_RATIO [16:19]
529 * UART5_RATIO [23:20]
531 ratio = readl(&clk->div_peril0);
532 ratio = (ratio >> (dev_index << 2)) & 0xf;
534 uclk = sclk / (ratio + 1);
539 /* exynos4x12: return uart clock frequency */
540 static unsigned long exynos4x12_get_uart_clk(int dev_index)
542 struct exynos4x12_clock *clk =
543 (struct exynos4x12_clock *)samsung_get_base_clock();
544 unsigned long uclk, sclk;
556 sel = readl(&clk->src_peril0);
557 sel = (sel >> (dev_index << 2)) & 0xf;
560 sclk = get_pll_clk(MPLL);
562 sclk = get_pll_clk(EPLL);
564 sclk = get_pll_clk(VPLL);
573 * UART3_RATIO [12:15]
574 * UART4_RATIO [16:19]
576 ratio = readl(&clk->div_peril0);
577 ratio = (ratio >> (dev_index << 2)) & 0xf;
579 uclk = sclk / (ratio + 1);
584 /* exynos5: return uart clock frequency */
585 static unsigned long exynos5_get_uart_clk(int dev_index)
587 struct exynos5_clock *clk =
588 (struct exynos5_clock *)samsung_get_base_clock();
589 unsigned long uclk, sclk;
602 sel = readl(&clk->src_peric0);
603 sel = (sel >> (dev_index << 2)) & 0xf;
606 sclk = get_pll_clk(MPLL);
608 sclk = get_pll_clk(EPLL);
610 sclk = get_pll_clk(VPLL);
619 * UART3_RATIO [12:15]
620 * UART4_RATIO [16:19]
621 * UART5_RATIO [23:20]
623 ratio = readl(&clk->div_peric0);
624 ratio = (ratio >> (dev_index << 2)) & 0xf;
626 uclk = sclk / (ratio + 1);
631 static unsigned long exynos4_get_mmc_clk(int dev_index)
633 struct exynos4_clock *clk =
634 (struct exynos4_clock *)samsung_get_base_clock();
635 unsigned long uclk, sclk;
636 unsigned int sel, ratio, pre_ratio;
639 sel = readl(&clk->src_fsys);
640 sel = (sel >> (dev_index << 2)) & 0xf;
643 sclk = get_pll_clk(MPLL);
645 sclk = get_pll_clk(EPLL);
647 sclk = get_pll_clk(VPLL);
654 ratio = readl(&clk->div_fsys1);
655 pre_ratio = readl(&clk->div_fsys1);
659 ratio = readl(&clk->div_fsys2);
660 pre_ratio = readl(&clk->div_fsys2);
663 ratio = readl(&clk->div_fsys3);
664 pre_ratio = readl(&clk->div_fsys3);
670 if (dev_index == 1 || dev_index == 3)
673 ratio = (ratio >> shift) & 0xf;
674 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
675 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
680 static unsigned long exynos5_get_mmc_clk(int dev_index)
682 struct exynos5_clock *clk =
683 (struct exynos5_clock *)samsung_get_base_clock();
684 unsigned long uclk, sclk;
685 unsigned int sel, ratio, pre_ratio;
688 sel = readl(&clk->src_fsys);
689 sel = (sel >> (dev_index << 2)) & 0xf;
692 sclk = get_pll_clk(MPLL);
694 sclk = get_pll_clk(EPLL);
696 sclk = get_pll_clk(VPLL);
703 ratio = readl(&clk->div_fsys1);
704 pre_ratio = readl(&clk->div_fsys1);
708 ratio = readl(&clk->div_fsys2);
709 pre_ratio = readl(&clk->div_fsys2);
715 if (dev_index == 1 || dev_index == 3)
718 ratio = (ratio >> shift) & 0xf;
719 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
720 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
725 /* exynos4: set the mmc clock */
726 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
728 struct exynos4_clock *clk =
729 (struct exynos4_clock *)samsung_get_base_clock();
735 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
737 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
739 * MMC4_PRE_RATIO [15:8]
742 addr = (unsigned int)&clk->div_fsys1;
743 } else if (dev_index == 4) {
744 addr = (unsigned int)&clk->div_fsys3;
747 addr = (unsigned int)&clk->div_fsys2;
752 val &= ~(0xff << ((dev_index << 4) + 8));
753 val |= (div & 0xff) << ((dev_index << 4) + 8);
757 /* exynos4x12: set the mmc clock */
758 static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
760 struct exynos4x12_clock *clk =
761 (struct exynos4x12_clock *)samsung_get_base_clock();
767 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
769 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
772 addr = (unsigned int)&clk->div_fsys1;
774 addr = (unsigned int)&clk->div_fsys2;
779 val &= ~(0xff << ((dev_index << 4) + 8));
780 val |= (div & 0xff) << ((dev_index << 4) + 8);
784 /* exynos5: set the mmc clock */
785 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
787 struct exynos5_clock *clk =
788 (struct exynos5_clock *)samsung_get_base_clock();
794 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
796 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
799 addr = (unsigned int)&clk->div_fsys1;
801 addr = (unsigned int)&clk->div_fsys2;
806 val &= ~(0xff << ((dev_index << 4) + 8));
807 val |= (div & 0xff) << ((dev_index << 4) + 8);
811 /* get_lcd_clk: return lcd clock frequency */
812 static unsigned long exynos4_get_lcd_clk(void)
814 struct exynos4_clock *clk =
815 (struct exynos4_clock *)samsung_get_base_clock();
816 unsigned long pclk, sclk;
824 sel = readl(&clk->src_lcd0);
833 sclk = get_pll_clk(MPLL);
835 sclk = get_pll_clk(EPLL);
837 sclk = get_pll_clk(VPLL);
845 ratio = readl(&clk->div_lcd0);
848 pclk = sclk / (ratio + 1);
853 /* get_lcd_clk: return lcd clock frequency */
854 static unsigned long exynos5_get_lcd_clk(void)
856 struct exynos5_clock *clk =
857 (struct exynos5_clock *)samsung_get_base_clock();
858 unsigned long pclk, sclk;
866 sel = readl(&clk->src_disp1_0);
875 sclk = get_pll_clk(MPLL);
877 sclk = get_pll_clk(EPLL);
879 sclk = get_pll_clk(VPLL);
887 ratio = readl(&clk->div_disp1_0);
890 pclk = sclk / (ratio + 1);
895 void exynos4_set_lcd_clk(void)
897 struct exynos4_clock *clk =
898 (struct exynos4_clock *)samsung_get_base_clock();
899 unsigned int cfg = 0;
911 cfg = readl(&clk->gate_block);
913 writel(cfg, &clk->gate_block);
919 * MDNIE_PWM0_SEL [8:11]
921 * set lcd0 src clock 0x6: SCLK_MPLL
923 cfg = readl(&clk->src_lcd0);
926 writel(cfg, &clk->src_lcd0);
936 * Gating all clocks for FIMD0
938 cfg = readl(&clk->gate_ip_lcd0);
940 writel(cfg, &clk->gate_ip_lcd0);
946 * MDNIE_PWM0_RATIO [11:8]
947 * MDNIE_PWM_PRE_RATIO [15:12]
948 * MIPI0_RATIO [19:16]
949 * MIPI0_PRE_RATIO [23:20]
954 writel(cfg, &clk->div_lcd0);
957 void exynos5_set_lcd_clk(void)
959 struct exynos5_clock *clk =
960 (struct exynos5_clock *)samsung_get_base_clock();
961 unsigned int cfg = 0;
973 cfg = readl(&clk->gate_block);
975 writel(cfg, &clk->gate_block);
981 * MDNIE_PWM0_SEL [8:11]
983 * set lcd0 src clock 0x6: SCLK_MPLL
985 cfg = readl(&clk->src_disp1_0);
988 writel(cfg, &clk->src_disp1_0);
998 * Gating all clocks for FIMD0
1000 cfg = readl(&clk->gate_ip_disp1);
1002 writel(cfg, &clk->gate_ip_disp1);
1007 * MDNIE0_RATIO [7:4]
1008 * MDNIE_PWM0_RATIO [11:8]
1009 * MDNIE_PWM_PRE_RATIO [15:12]
1010 * MIPI0_RATIO [19:16]
1011 * MIPI0_PRE_RATIO [23:20]
1016 writel(cfg, &clk->div_disp1_0);
1019 void exynos4_set_mipi_clk(void)
1021 struct exynos4_clock *clk =
1022 (struct exynos4_clock *)samsung_get_base_clock();
1023 unsigned int cfg = 0;
1029 * MDNIE_PWM0_SEL [8:11]
1031 * set mipi0 src clock 0x6: SCLK_MPLL
1033 cfg = readl(&clk->src_lcd0);
1034 cfg &= ~(0xf << 12);
1036 writel(cfg, &clk->src_lcd0);
1042 * MDNIE_PWM0_MASK [8]
1044 * set src mask mipi0 0x1: Unmask
1046 cfg = readl(&clk->src_mask_lcd0);
1048 writel(cfg, &clk->src_mask_lcd0);
1058 * Gating all clocks for MIPI0
1060 cfg = readl(&clk->gate_ip_lcd0);
1062 writel(cfg, &clk->gate_ip_lcd0);
1067 * MDNIE0_RATIO [7:4]
1068 * MDNIE_PWM0_RATIO [11:8]
1069 * MDNIE_PWM_PRE_RATIO [15:12]
1070 * MIPI0_RATIO [19:16]
1071 * MIPI0_PRE_RATIO [23:20]
1074 cfg &= ~(0xf << 16);
1076 writel(cfg, &clk->div_lcd0);
1082 * exynos5: obtaining the I2C clock
1084 static unsigned long exynos5_get_i2c_clk(void)
1086 struct exynos5_clock *clk =
1087 (struct exynos5_clock *)samsung_get_base_clock();
1088 unsigned long aclk_66, aclk_66_pre, sclk;
1091 sclk = get_pll_clk(MPLL);
1093 ratio = (readl(&clk->div_top1)) >> 24;
1095 aclk_66_pre = sclk / (ratio + 1);
1096 ratio = readl(&clk->div_top0);
1098 aclk_66 = aclk_66_pre / (ratio + 1);
1102 int exynos5_set_epll_clk(unsigned long rate)
1104 unsigned int epll_con, epll_con_k;
1106 unsigned int lockcnt;
1108 struct exynos5_clock *clk =
1109 (struct exynos5_clock *)samsung_get_base_clock();
1111 epll_con = readl(&clk->epll_con0);
1112 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1113 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1114 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1115 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1116 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1118 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1119 if (exynos5_epll_div[i].freq_out == rate)
1123 if (i == ARRAY_SIZE(exynos5_epll_div))
1126 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1127 epll_con |= exynos5_epll_div[i].en_lock_det <<
1128 EPLL_CON0_LOCK_DET_EN_SHIFT;
1129 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1130 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1131 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1134 * Required period ( in cycles) to genarate a stable clock output.
1135 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1136 * frequency input (as per spec)
1138 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1140 writel(lockcnt, &clk->epll_lock);
1141 writel(epll_con, &clk->epll_con0);
1142 writel(epll_con_k, &clk->epll_con1);
1144 start = get_timer(0);
1146 while (!(readl(&clk->epll_con0) &
1147 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1148 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1149 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1156 void exynos5_set_i2s_clk_source(void)
1158 struct exynos5_clock *clk =
1159 (struct exynos5_clock *)samsung_get_base_clock();
1161 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1162 (CLK_SRC_SCLK_EPLL));
1165 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1166 unsigned int dst_frq)
1168 struct exynos5_clock *clk =
1169 (struct exynos5_clock *)samsung_get_base_clock();
1172 if ((dst_frq == 0) || (src_frq == 0)) {
1173 debug("%s: Invalid requency input for prescaler\n", __func__);
1174 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1178 div = (src_frq / dst_frq);
1179 if (div > AUDIO_1_RATIO_MASK) {
1180 debug("%s: Frequency ratio is out of range\n", __func__);
1181 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1184 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1185 (div & AUDIO_1_RATIO_MASK));
1190 * Linearly searches for the most accurate main and fine stage clock scalars
1191 * (divisors) for a specified target frequency and scalar bit sizes by checking
1192 * all multiples of main_scalar_bits values. Will always return scalars up to or
1193 * slower than target.
1195 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1196 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1197 * @param input_freq Clock frequency to be scaled in Hz
1198 * @param target_freq Desired clock frequency in Hz
1199 * @param best_fine_scalar Pointer to store the fine stage divisor
1201 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1204 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1205 unsigned int fine_scalar_bits, unsigned int input_rate,
1206 unsigned int target_rate, unsigned int *best_fine_scalar)
1209 int best_main_scalar = -1;
1210 unsigned int best_error = target_rate;
1211 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1212 const unsigned int loops = 1 << main_scaler_bits;
1214 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1217 assert(best_fine_scalar != NULL);
1218 assert(main_scaler_bits <= fine_scalar_bits);
1220 *best_fine_scalar = 1;
1222 if (input_rate == 0 || target_rate == 0)
1225 if (target_rate >= input_rate)
1228 for (i = 1; i <= loops; i++) {
1229 const unsigned int effective_div = max(min(input_rate / i /
1230 target_rate, cap), 1);
1231 const unsigned int effective_rate = input_rate / i /
1233 const int error = target_rate - effective_rate;
1235 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1236 effective_rate, error);
1238 if (error >= 0 && error <= best_error) {
1240 best_main_scalar = i;
1241 *best_fine_scalar = effective_div;
1245 return best_main_scalar;
1248 static int exynos5_set_spi_clk(enum periph_id periph_id,
1251 struct exynos5_clock *clk =
1252 (struct exynos5_clock *)samsung_get_base_clock();
1255 unsigned shift, pre_shift;
1256 unsigned mask = 0xff;
1259 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1261 debug("%s: Cannot set clock rate for periph %d",
1262 __func__, periph_id);
1268 switch (periph_id) {
1269 case PERIPH_ID_SPI0:
1270 reg = &clk->div_peric1;
1274 case PERIPH_ID_SPI1:
1275 reg = &clk->div_peric1;
1279 case PERIPH_ID_SPI2:
1280 reg = &clk->div_peric2;
1284 case PERIPH_ID_SPI3:
1285 reg = &clk->sclk_div_isp;
1289 case PERIPH_ID_SPI4:
1290 reg = &clk->sclk_div_isp;
1295 debug("%s: Unsupported peripheral ID %d\n", __func__,
1299 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1300 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1305 static unsigned long exynos4_get_i2c_clk(void)
1307 struct exynos4_clock *clk =
1308 (struct exynos4_clock *)samsung_get_base_clock();
1309 unsigned long sclk, aclk_100;
1312 sclk = get_pll_clk(APLL);
1314 ratio = (readl(&clk->div_top)) >> 4;
1316 aclk_100 = sclk / (ratio + 1);
1320 unsigned long get_pll_clk(int pllreg)
1322 if (cpu_is_exynos5())
1323 return exynos5_get_pll_clk(pllreg);
1325 if (proid_is_exynos4412())
1326 return exynos4x12_get_pll_clk(pllreg);
1327 return exynos4_get_pll_clk(pllreg);
1331 unsigned long get_arm_clk(void)
1333 if (cpu_is_exynos5())
1334 return exynos5_get_arm_clk();
1336 if (proid_is_exynos4412())
1337 return exynos4x12_get_arm_clk();
1338 return exynos4_get_arm_clk();
1342 unsigned long get_i2c_clk(void)
1344 if (cpu_is_exynos5()) {
1345 return exynos5_get_i2c_clk();
1346 } else if (cpu_is_exynos4()) {
1347 return exynos4_get_i2c_clk();
1349 debug("I2C clock is not set for this CPU\n");
1354 unsigned long get_pwm_clk(void)
1356 if (cpu_is_exynos5())
1357 return exynos5_get_pwm_clk();
1359 if (proid_is_exynos4412())
1360 return exynos4x12_get_pwm_clk();
1361 return exynos4_get_pwm_clk();
1365 unsigned long get_uart_clk(int dev_index)
1367 if (cpu_is_exynos5())
1368 return exynos5_get_uart_clk(dev_index);
1370 if (proid_is_exynos4412())
1371 return exynos4x12_get_uart_clk(dev_index);
1372 return exynos4_get_uart_clk(dev_index);
1376 unsigned long get_mmc_clk(int dev_index)
1378 if (cpu_is_exynos5())
1379 return exynos5_get_mmc_clk(dev_index);
1381 return exynos4_get_mmc_clk(dev_index);
1384 void set_mmc_clk(int dev_index, unsigned int div)
1386 if (cpu_is_exynos5())
1387 exynos5_set_mmc_clk(dev_index, div);
1389 if (proid_is_exynos4412())
1390 exynos4x12_set_mmc_clk(dev_index, div);
1391 exynos4_set_mmc_clk(dev_index, div);
1395 unsigned long get_lcd_clk(void)
1397 if (cpu_is_exynos4())
1398 return exynos4_get_lcd_clk();
1400 return exynos5_get_lcd_clk();
1403 void set_lcd_clk(void)
1405 if (cpu_is_exynos4())
1406 exynos4_set_lcd_clk();
1408 exynos5_set_lcd_clk();
1411 void set_mipi_clk(void)
1413 if (cpu_is_exynos4())
1414 exynos4_set_mipi_clk();
1417 int set_spi_clk(int periph_id, unsigned int rate)
1419 if (cpu_is_exynos5())
1420 return exynos5_set_spi_clk(periph_id, rate);
1425 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
1428 if (cpu_is_exynos5())
1429 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
1434 void set_i2s_clk_source(void)
1436 if (cpu_is_exynos5())
1437 exynos5_set_i2s_clk_source();
1440 int set_epll_clk(unsigned long rate)
1442 if (cpu_is_exynos5())
1443 return exynos5_set_epll_clk(rate);