arch/arm/cpu/armv7/am33xx/emif4.c

   1 /*
   2  * emif4.c
   3  *
   4  * AM33XX emif4 configuration file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/ddr_defs.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/io.h>
  18 #include <asm/emif.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 int dram_init(void)
  23 {
  24         /* dram_init must store complete ramsize in gd->ram_size */
  25         gd->ram_size = get_ram_size(
  26                         (void *)CONFIG_SYS_SDRAM_BASE,
  27                         CONFIG_MAX_RAM_BANK_SIZE);
  28         return 0;
  29 }
  30
  31 void dram_init_banksize(void)
  32 {
  33         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  34         gd->bd->bi_dram[0].size = gd->ram_size;
  35 }
  36
  37
  38 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
  39 #ifdef CONFIG_TI81XX
  40 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
  41                                 (struct dmm_lisa_map_regs *)DMM_BASE;
  42 #endif
  43 static struct vtp_reg *vtpreg[2] = {
  44                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
  45                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
  46 #ifdef CONFIG_AM33XX
  47 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  48 #endif
  49
  50 #ifdef CONFIG_TI81XX
  51 void config_dmm(const struct dmm_lisa_map_regs *regs)
  52 {
  53         enable_dmm_clocks();
  54
  55         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  56         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  57         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  58         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  59
  60         writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
  61         writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
  62         writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
  63         writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
  64 }
  65 #endif
  66
  67 static void config_vtp(int nr)
  68 {
  69         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  70                         &vtpreg[nr]->vtp0ctrlreg);
  71         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  72                         &vtpreg[nr]->vtp0ctrlreg);
  73         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
  74                         &vtpreg[nr]->vtp0ctrlreg);
  75
  76         /* Poll for READY */
  77         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
  78                         VTP_CTRL_READY)
  79                 ;
  80 }
  81
  82 void __weak ddr_pll_config(unsigned int ddrpll_m)
  83 {
  84 }
  85
  86 void config_ddr(unsigned int pll, unsigned int ioctrl,
  87                 const struct ddr_data *data, const struct cmd_control *ctrl,
  88                 const struct emif_regs *regs, int nr)
  89 {
  90         ddr_pll_config(pll);
  91         config_vtp(nr);
  92         config_cmd_ctrl(ctrl, nr);
  93
  94         config_ddr_data(data, nr);
  95 #ifdef CONFIG_AM33XX
  96         config_io_ctrl(ioctrl);
  97
  98         /* Set CKE to be controlled by EMIF/DDR PHY */
  99         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 100 #endif
 101
 102         /* Program EMIF instance */
 103         config_ddr_phy(regs, nr);
 104         set_sdram_timings(regs, nr);
 105         config_sdram(regs, nr);
 106 }
 107 #endif