2 * DDR Configuration for AM33xx devices.
4 * Copyright (C) 2011 Texas Instruments Incorporated -
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/ddr_defs.h>
24 * Base address for EMIF instances
26 static struct emif_reg_struct *emif_reg = {
27 (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
30 * Base address for DDR instance
32 static struct ddr_regs *ddr_reg[2] = {
33 (struct ddr_regs *)DDR_PHY_BASE_ADDR,
34 (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
37 * Base address for ddr io control instances
39 static struct ddr_cmdtctrl *ioctrl_reg = {
40 (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
45 void config_sdram(struct sdram_config *cfg)
47 writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
48 writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
49 writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
55 void set_sdram_timings(struct sdram_timing *t)
57 writel(t->time1, &emif_reg->emif_sdram_tim_1);
58 writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
59 writel(t->time2, &emif_reg->emif_sdram_tim_2);
60 writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
61 writel(t->time3, &emif_reg->emif_sdram_tim_3);
62 writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
68 void config_ddr_phy(struct ddr_phy_control *p)
70 writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
71 writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
75 * Configure DDR CMD control registers
77 void config_cmd_ctrl(const struct cmd_control *cmd)
79 writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
80 writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
81 writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
82 writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
83 writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
85 writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
86 writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
87 writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
88 writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
89 writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
91 writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
92 writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
93 writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
94 writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
95 writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
99 * Configure DDR DATA registers
101 void config_ddr_data(int macrono, const struct ddr_data *data)
103 writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
104 writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
106 writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
107 writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
109 writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
110 writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
111 writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
112 writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
114 writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
115 writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
117 writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
118 writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
120 writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
123 void config_io_ctrl(struct ddr_ioctrl *ioctrl)
125 writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
126 writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
127 writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
128 writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
129 writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);