arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated -
   5 http://www.ti.com/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22
  23 /**
  24  * Base address for EMIF instances
  25  */
  26 static struct emif_reg_struct *emif_reg = {
  27                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
  28
  29 /**
  30  * Base address for DDR instance
  31  */
  32 static struct ddr_regs *ddr_reg[2] = {
  33                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR,
  34                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
  35
  36 /**
  37  * Base address for ddr io control instances
  38  */
  39 static struct ddr_cmdtctrl *ioctrl_reg = {
  40                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  41
  42 /**
  43  * Configure SDRAM
  44  */
  45 void config_sdram(const struct emif_regs *regs)
  46 {
  47         writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
  48         writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
  49         writel(regs->sdram_config, &emif_reg->emif_sdram_config);
  50 }
  51
  52 /**
  53  * Set SDRAM timings
  54  */
  55 void set_sdram_timings(const struct emif_regs *regs)
  56 {
  57         writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
  58         writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
  59         writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
  60         writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
  61         writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
  62         writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
  63 }
  64
  65 /**
  66  * Configure DDR PHY
  67  */
  68 void config_ddr_phy(const struct emif_regs *regs)
  69 {
  70         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
  71         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
  72 }
  73
  74 /**
  75  * Configure DDR CMD control registers
  76  */
  77 void config_cmd_ctrl(const struct cmd_control *cmd)
  78 {
  79         writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
  80         writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
  81         writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
  82         writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
  83         writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
  84
  85         writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
  86         writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
  87         writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
  88         writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
  89         writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
  90
  91         writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
  92         writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
  93         writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
  94         writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
  95         writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
  96 }
  97
  98 /**
  99  * Configure DDR DATA registers
 100  */
 101 void config_ddr_data(int macrono, const struct ddr_data *data)
 102 {
 103         writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
 104         writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
 105         writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
 106         writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
 107         writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
 108         writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
 109         writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 110 }
 111
 112 void config_io_ctrl(unsigned long val)
 113 {
 114         writel(val, &ioctrl_reg->cm0ioctl);
 115         writel(val, &ioctrl_reg->cm1ioctl);
 116         writel(val, &ioctrl_reg->cm2ioctl);
 117         writel(val, &ioctrl_reg->dt0ioctl);
 118         writel(val, &ioctrl_reg->dt1ioctl);
 119 }