2 * DDR Configuration for AM33xx devices.
4 * Copyright (C) 2011 Texas Instruments Incorporated -
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/ddr_defs.h>
23 * Base address for EMIF instances
25 static struct emif_regs *emif_reg = {
26 (struct emif_regs *)EMIF4_0_CFG_BASE};
29 * Base address for DDR instance
31 static struct ddr_regs *ddr_reg[2] = {
32 (struct ddr_regs *)DDR_PHY_BASE_ADDR,
33 (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
36 * Base address for ddr io control instances
38 static struct ddr_cmdtctrl *ioctrl_reg = {
39 (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
42 * As a convention, all functions here return 0 on success
49 int config_sdram(struct sdram_config *cfg)
51 writel(cfg->sdrcr, &emif_reg->sdrcr);
52 writel(cfg->sdrcr2, &emif_reg->sdrcr2);
53 writel(cfg->refresh, &emif_reg->sdrrcr);
54 writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
62 int set_sdram_timings(struct sdram_timing *t)
64 writel(t->time1, &emif_reg->sdrtim1);
65 writel(t->time1_sh, &emif_reg->sdrtim1sr);
66 writel(t->time2, &emif_reg->sdrtim2);
67 writel(t->time2_sh, &emif_reg->sdrtim2sr);
68 writel(t->time3, &emif_reg->sdrtim3);
69 writel(t->time3_sh, &emif_reg->sdrtim3sr);
77 int config_ddr_phy(struct ddr_phy_control *p)
79 writel(p->reg, &emif_reg->ddrphycr);
80 writel(p->reg_sh, &emif_reg->ddrphycsr);
86 * Configure DDR CMD control registers
88 int config_cmd_ctrl(struct cmd_control *cmd)
90 writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
91 writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
92 writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
93 writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
94 writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
96 writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
97 writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
98 writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
99 writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
100 writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
102 writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
103 writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
104 writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
105 writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
106 writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
112 * Configure DDR DATA registers
114 int config_ddr_data(int macrono, struct ddr_data *data)
116 writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
117 writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
119 writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
120 writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
122 writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
123 writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
124 writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
125 writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
127 writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
128 writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
130 writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
131 writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
133 writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
138 int config_io_ctrl(struct ddr_ioctrl *ioctrl)
140 writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
141 writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
142 writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
143 writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
144 writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);