4 * clocks for AM43XX based boards
5 * Derived from AM33XX based boards
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
19 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
20 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
21 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
23 const struct dpll_regs dpll_mpu_regs = {
24 .cm_clkmode_dpll = CM_WKUP + 0x560,
25 .cm_idlest_dpll = CM_WKUP + 0x564,
26 .cm_clksel_dpll = CM_WKUP + 0x56c,
27 .cm_div_m2_dpll = CM_WKUP + 0x570,
30 const struct dpll_regs dpll_core_regs = {
31 .cm_clkmode_dpll = CM_WKUP + 0x520,
32 .cm_idlest_dpll = CM_WKUP + 0x524,
33 .cm_clksel_dpll = CM_WKUP + 0x52C,
34 .cm_div_m4_dpll = CM_WKUP + 0x538,
35 .cm_div_m5_dpll = CM_WKUP + 0x53C,
36 .cm_div_m6_dpll = CM_WKUP + 0x540,
39 const struct dpll_regs dpll_per_regs = {
40 .cm_clkmode_dpll = CM_WKUP + 0x5E0,
41 .cm_idlest_dpll = CM_WKUP + 0x5E4,
42 .cm_clksel_dpll = CM_WKUP + 0x5EC,
43 .cm_div_m2_dpll = CM_WKUP + 0x5F0,
46 const struct dpll_regs dpll_ddr_regs = {
47 .cm_clkmode_dpll = CM_WKUP + 0x5A0,
48 .cm_idlest_dpll = CM_WKUP + 0x5A4,
49 .cm_clksel_dpll = CM_WKUP + 0x5AC,
50 .cm_div_m2_dpll = CM_WKUP + 0x5B0,
53 const struct dpll_params dpll_mpu = {
54 -1, -1, -1, -1, -1, -1, -1};
55 const struct dpll_params dpll_core = {
56 -1, -1, -1, -1, -1, -1, -1};
57 const struct dpll_params dpll_per = {
58 -1, -1, -1, -1, -1, -1, -1};
60 void setup_clocks_for_console(void)
62 /* Do not add any spl_debug prints in this function */
63 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
64 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
65 CD_CLKCTRL_CLKTRCTRL_SHIFT);
68 clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
69 MODULE_CLKCTRL_MODULEMODE_MASK,
70 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
71 MODULE_CLKCTRL_MODULEMODE_SHIFT);
74 void enable_basic_clocks(void)
76 u32 *const clk_domains[] = {
79 &cmper->l4lsclkstctrl,
81 &cmper->emifclkstctrl,
85 u32 *const clk_modules_explicit_en[] = {
89 &cmwkup->wkl4wkclkctrl,
90 &cmper->l3instrclkctrl,
92 &cmwkup->wkgpio0clkctrl,
93 &cmwkup->wkctrlclkctrl,
94 &cmper->timer2clkctrl,
99 &cmwkup->wkup_i2c0ctrl,
100 &cmper->gpio1clkctrl,
101 &cmper->gpio2clkctrl,
102 &cmper->gpio3clkctrl,
104 &cmper->emiffwclkctrl,
106 &cmper->otfaemifclkctrl,
110 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
112 /* Select the Master osc clk as Timer2 clock source */
113 writel(0x1, &cmdpll->clktimer2clk);