4 * clocks for AM33XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
17 #define OSC (V_OSCK/1000000)
19 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
20 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
21 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
22 struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
24 const struct dpll_regs dpll_mpu_regs = {
25 .cm_clkmode_dpll = CM_WKUP + 0x88,
26 .cm_idlest_dpll = CM_WKUP + 0x20,
27 .cm_clksel_dpll = CM_WKUP + 0x2C,
28 .cm_div_m2_dpll = CM_WKUP + 0xA8,
31 const struct dpll_regs dpll_core_regs = {
32 .cm_clkmode_dpll = CM_WKUP + 0x90,
33 .cm_idlest_dpll = CM_WKUP + 0x5C,
34 .cm_clksel_dpll = CM_WKUP + 0x68,
35 .cm_div_m4_dpll = CM_WKUP + 0x80,
36 .cm_div_m5_dpll = CM_WKUP + 0x84,
37 .cm_div_m6_dpll = CM_WKUP + 0xD8,
40 const struct dpll_regs dpll_per_regs = {
41 .cm_clkmode_dpll = CM_WKUP + 0x8C,
42 .cm_idlest_dpll = CM_WKUP + 0x70,
43 .cm_clksel_dpll = CM_WKUP + 0x9C,
44 .cm_div_m2_dpll = CM_WKUP + 0xAC,
47 const struct dpll_regs dpll_ddr_regs = {
48 .cm_clkmode_dpll = CM_WKUP + 0x94,
49 .cm_idlest_dpll = CM_WKUP + 0x34,
50 .cm_clksel_dpll = CM_WKUP + 0x40,
51 .cm_div_m2_dpll = CM_WKUP + 0xA0,
54 const struct dpll_params dpll_mpu = {
55 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
56 const struct dpll_params dpll_core = {
57 1000, OSC-1, -1, -1, 10, 8, 4};
58 const struct dpll_params dpll_per = {
59 960, OSC-1, 5, -1, -1, -1, -1};
61 void setup_clocks_for_console(void)
63 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
64 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
65 CD_CLKCTRL_CLKTRCTRL_SHIFT);
67 clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
68 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
69 CD_CLKCTRL_CLKTRCTRL_SHIFT);
71 clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
72 MODULE_CLKCTRL_MODULEMODE_MASK,
73 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
74 MODULE_CLKCTRL_MODULEMODE_SHIFT);
75 clrsetbits_le32(&cmper->uart1clkctrl,
76 MODULE_CLKCTRL_MODULEMODE_MASK,
77 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
78 MODULE_CLKCTRL_MODULEMODE_SHIFT);
79 clrsetbits_le32(&cmper->uart2clkctrl,
80 MODULE_CLKCTRL_MODULEMODE_MASK,
81 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
82 MODULE_CLKCTRL_MODULEMODE_SHIFT);
83 clrsetbits_le32(&cmper->uart3clkctrl,
84 MODULE_CLKCTRL_MODULEMODE_MASK,
85 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
86 MODULE_CLKCTRL_MODULEMODE_SHIFT);
87 clrsetbits_le32(&cmper->uart4clkctrl,
88 MODULE_CLKCTRL_MODULEMODE_MASK,
89 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
90 MODULE_CLKCTRL_MODULEMODE_SHIFT);
91 clrsetbits_le32(&cmper->uart5clkctrl,
92 MODULE_CLKCTRL_MODULEMODE_MASK,
93 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
94 MODULE_CLKCTRL_MODULEMODE_SHIFT);
97 void enable_basic_clocks(void)
99 u32 *const clk_domains[] = {
101 &cmper->l4fwclkstctrl,
102 &cmper->l3sclkstctrl,
103 &cmper->l4lsclkstctrl,
104 &cmwkup->wkclkstctrl,
105 &cmper->emiffwclkctrl,
110 u32 *const clk_modules_explicit_en[] = {
114 &cmwkup->wkl4wkclkctrl,
115 &cmper->l3instrclkctrl,
117 &cmwkup->wkgpio0clkctrl,
118 &cmwkup->wkctrlclkctrl,
119 &cmper->timer2clkctrl,
124 &cmwkup->wkup_i2c0ctrl,
125 &cmper->gpio1clkctrl,
126 &cmper->gpio2clkctrl,
127 &cmper->gpio3clkctrl,
129 &cmper->cpgmac0clkctrl,
133 &cmper->emiffwclkctrl,
138 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
140 /* Select the Master osc 24 MHZ as Timer2 clock source */
141 writel(0x1, &cmdpll->clktimer2clk);