4 * clocks for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/hardware.h>
25 #define PRCM_MOD_EN 0x2
26 #define PRCM_FORCE_WAKEUP 0x2
27 #define PRCM_FUNCTL 0x0
29 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
30 #define PRCM_L3_GCLK_ACTIVITY BIT(4)
32 #define PLL_BYPASS_MODE 0x4
33 #define ST_MN_BYPASS 0x00000100
34 #define ST_DPLL_CLK 0x00000001
35 #define CLK_SEL_MASK 0x7ffff
36 #define CLK_DIV_MASK 0x1f
37 #define CLK_DIV2_MASK 0x7f
38 #define CLK_SEL_SHIFT 0x8
39 #define CLK_MODE_SEL 0x7
40 #define CLK_MODE_MASK 0xfffffff8
41 #define CLK_DIV_SEL 0xFFFFFFE0
42 #define CPGMAC0_IDLE 0x30000
44 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
45 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
46 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
48 static void enable_interface_clocks(void)
50 /* Enable all the Interconnect Modules */
51 writel(PRCM_MOD_EN, &cmper->l3clkctrl);
52 while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
55 writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
56 while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
59 writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
60 while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
63 writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
64 while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
67 writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
68 while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
71 writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
72 while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
77 * Force power domain wake up transition
78 * Ensure that the corresponding interface clock is active before
79 * using the peripheral
81 static void power_domain_wkup_transition(void)
83 writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
84 writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
85 writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
86 writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
87 writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
91 * Enable the peripheral clock for required peripherals
93 static void enable_per_clocks(void)
95 /* Enable the control module though RBL would have done it*/
96 writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
97 while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
100 /* Enable the module clock */
101 writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
102 while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
105 /* Select the Master osc 24 MHZ as Timer2 clock source */
106 writel(0x1, &cmdpll->clktimer2clk);
109 writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
110 while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
114 writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
115 while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
119 writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
120 while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
124 writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
125 while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
129 writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
130 while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
134 writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
135 while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
139 writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
140 while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
144 writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
145 while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
149 static void mpu_pll_config(void)
151 u32 clkmode, clksel, div_m2;
153 clkmode = readl(&cmwkup->clkmoddpllmpu);
154 clksel = readl(&cmwkup->clkseldpllmpu);
155 div_m2 = readl(&cmwkup->divm2dpllmpu);
157 /* Set the PLL to bypass Mode */
158 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
159 while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
162 clksel = clksel & (~CLK_SEL_MASK);
163 clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
164 writel(clksel, &cmwkup->clkseldpllmpu);
166 div_m2 = div_m2 & ~CLK_DIV_MASK;
167 div_m2 = div_m2 | MPUPLL_M2;
168 writel(div_m2, &cmwkup->divm2dpllmpu);
170 clkmode = clkmode | CLK_MODE_SEL;
171 writel(clkmode, &cmwkup->clkmoddpllmpu);
173 while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
177 static void core_pll_config(void)
179 u32 clkmode, clksel, div_m4, div_m5, div_m6;
181 clkmode = readl(&cmwkup->clkmoddpllcore);
182 clksel = readl(&cmwkup->clkseldpllcore);
183 div_m4 = readl(&cmwkup->divm4dpllcore);
184 div_m5 = readl(&cmwkup->divm5dpllcore);
185 div_m6 = readl(&cmwkup->divm6dpllcore);
187 /* Set the PLL to bypass Mode */
188 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
190 while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
193 clksel = clksel & (~CLK_SEL_MASK);
194 clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
195 writel(clksel, &cmwkup->clkseldpllcore);
197 div_m4 = div_m4 & ~CLK_DIV_MASK;
198 div_m4 = div_m4 | COREPLL_M4;
199 writel(div_m4, &cmwkup->divm4dpllcore);
201 div_m5 = div_m5 & ~CLK_DIV_MASK;
202 div_m5 = div_m5 | COREPLL_M5;
203 writel(div_m5, &cmwkup->divm5dpllcore);
205 div_m6 = div_m6 & ~CLK_DIV_MASK;
206 div_m6 = div_m6 | COREPLL_M6;
207 writel(div_m6, &cmwkup->divm6dpllcore);
209 clkmode = clkmode | CLK_MODE_SEL;
210 writel(clkmode, &cmwkup->clkmoddpllcore);
212 while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
216 static void per_pll_config(void)
218 u32 clkmode, clksel, div_m2;
220 clkmode = readl(&cmwkup->clkmoddpllper);
221 clksel = readl(&cmwkup->clkseldpllper);
222 div_m2 = readl(&cmwkup->divm2dpllper);
224 /* Set the PLL to bypass Mode */
225 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
227 while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
230 clksel = clksel & (~CLK_SEL_MASK);
231 clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
232 writel(clksel, &cmwkup->clkseldpllper);
234 div_m2 = div_m2 & ~CLK_DIV2_MASK;
235 div_m2 = div_m2 | PERPLL_M2;
236 writel(div_m2, &cmwkup->divm2dpllper);
238 clkmode = clkmode | CLK_MODE_SEL;
239 writel(clkmode, &cmwkup->clkmoddpllper);
241 while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
245 static void ddr_pll_config(void)
247 u32 clkmode, clksel, div_m2;
249 clkmode = readl(&cmwkup->clkmoddpllddr);
250 clksel = readl(&cmwkup->clkseldpllddr);
251 div_m2 = readl(&cmwkup->divm2dpllddr);
253 /* Set the PLL to bypass Mode */
254 clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
255 writel(clkmode, &cmwkup->clkmoddpllddr);
257 /* Wait till bypass mode is enabled */
258 while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
262 clksel = clksel & (~CLK_SEL_MASK);
263 clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
264 writel(clksel, &cmwkup->clkseldpllddr);
266 div_m2 = div_m2 & CLK_DIV_SEL;
267 div_m2 = div_m2 | DDRPLL_M2;
268 writel(div_m2, &cmwkup->divm2dpllddr);
270 clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
271 writel(clkmode, &cmwkup->clkmoddpllddr);
273 /* Wait till dpll is locked */
274 while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
278 void enable_emif_clocks(void)
280 /* Enable the EMIF_FW Functional clock */
281 writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
282 /* Enable EMIF0 Clock */
283 writel(PRCM_MOD_EN, &cmper->emifclkctrl);
284 /* Poll for emif_gclk & L3_G clock are active */
285 while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
286 PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
287 PRCM_L3_GCLK_ACTIVITY))
289 /* Poll if module is functional */
290 while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
295 * Configure the PLL/PRCM for necessary peripherals
304 /* Enable the required interconnect clocks */
305 enable_interface_clocks();
307 /* Power domain wake up transition */
308 power_domain_wkup_transition();
310 /* Enable the required peripherals */