4 * clocks for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/hardware.h>
25 #define PRCM_MOD_EN 0x2
26 #define PRCM_FORCE_WAKEUP 0x2
27 #define PRCM_FUNCTL 0x0
29 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
30 #define PRCM_L3_GCLK_ACTIVITY BIT(4)
32 #define PLL_BYPASS_MODE 0x4
33 #define ST_MN_BYPASS 0x00000100
34 #define ST_DPLL_CLK 0x00000001
35 #define CLK_SEL_MASK 0x7ffff
36 #define CLK_DIV_MASK 0x1f
37 #define CLK_DIV2_MASK 0x7f
38 #define CLK_SEL_SHIFT 0x8
39 #define CLK_MODE_SEL 0x7
40 #define CLK_MODE_MASK 0xfffffff8
41 #define CLK_DIV_SEL 0xFFFFFFE0
42 #define CPGMAC0_IDLE 0x30000
44 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
45 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
46 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
47 const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
49 static void enable_interface_clocks(void)
51 /* Enable all the Interconnect Modules */
52 writel(PRCM_MOD_EN, &cmper->l3clkctrl);
53 while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
56 writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
57 while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
60 writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
61 while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
64 writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
65 while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
68 writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
69 while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
72 writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
73 while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
76 writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
77 while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
82 * Force power domain wake up transition
83 * Ensure that the corresponding interface clock is active before
84 * using the peripheral
86 static void power_domain_wkup_transition(void)
88 writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
89 writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
90 writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
91 writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
92 writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
96 * Enable the peripheral clock for required peripherals
98 static void enable_per_clocks(void)
100 /* Enable the control module though RBL would have done it*/
101 writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
102 while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
105 /* Enable the module clock */
106 writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
107 while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
110 /* Select the Master osc 24 MHZ as Timer2 clock source */
111 writel(0x1, &cmdpll->clktimer2clk);
114 writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
115 while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
119 #ifdef CONFIG_SERIAL2
120 writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
121 while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
123 #endif /* CONFIG_SERIAL2 */
126 #ifdef CONFIG_SERIAL3
127 writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
128 while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
130 #endif /* CONFIG_SERIAL3 */
133 #ifdef CONFIG_SERIAL4
134 writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
135 while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
137 #endif /* CONFIG_SERIAL4 */
140 #ifdef CONFIG_SERIAL5
141 writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
142 while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
144 #endif /* CONFIG_SERIAL5 */
147 #ifdef CONFIG_SERIAL6
148 writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
149 while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
151 #endif /* CONFIG_SERIAL6 */
154 writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
155 while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
159 writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
160 while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
164 writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
165 while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
169 writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
170 while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
174 writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
175 while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
179 writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
180 while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
184 writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
185 while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
189 writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
190 while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
194 writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
195 while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
199 static void mpu_pll_config(void)
201 u32 clkmode, clksel, div_m2;
203 clkmode = readl(&cmwkup->clkmoddpllmpu);
204 clksel = readl(&cmwkup->clkseldpllmpu);
205 div_m2 = readl(&cmwkup->divm2dpllmpu);
207 /* Set the PLL to bypass Mode */
208 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
209 while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
212 clksel = clksel & (~CLK_SEL_MASK);
213 clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
214 writel(clksel, &cmwkup->clkseldpllmpu);
216 div_m2 = div_m2 & ~CLK_DIV_MASK;
217 div_m2 = div_m2 | MPUPLL_M2;
218 writel(div_m2, &cmwkup->divm2dpllmpu);
220 clkmode = clkmode | CLK_MODE_SEL;
221 writel(clkmode, &cmwkup->clkmoddpllmpu);
223 while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
227 static void core_pll_config(void)
229 u32 clkmode, clksel, div_m4, div_m5, div_m6;
231 clkmode = readl(&cmwkup->clkmoddpllcore);
232 clksel = readl(&cmwkup->clkseldpllcore);
233 div_m4 = readl(&cmwkup->divm4dpllcore);
234 div_m5 = readl(&cmwkup->divm5dpllcore);
235 div_m6 = readl(&cmwkup->divm6dpllcore);
237 /* Set the PLL to bypass Mode */
238 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
240 while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
243 clksel = clksel & (~CLK_SEL_MASK);
244 clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
245 writel(clksel, &cmwkup->clkseldpllcore);
247 div_m4 = div_m4 & ~CLK_DIV_MASK;
248 div_m4 = div_m4 | COREPLL_M4;
249 writel(div_m4, &cmwkup->divm4dpllcore);
251 div_m5 = div_m5 & ~CLK_DIV_MASK;
252 div_m5 = div_m5 | COREPLL_M5;
253 writel(div_m5, &cmwkup->divm5dpllcore);
255 div_m6 = div_m6 & ~CLK_DIV_MASK;
256 div_m6 = div_m6 | COREPLL_M6;
257 writel(div_m6, &cmwkup->divm6dpllcore);
259 clkmode = clkmode | CLK_MODE_SEL;
260 writel(clkmode, &cmwkup->clkmoddpllcore);
262 while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
266 static void per_pll_config(void)
268 u32 clkmode, clksel, div_m2;
270 clkmode = readl(&cmwkup->clkmoddpllper);
271 clksel = readl(&cmwkup->clkseldpllper);
272 div_m2 = readl(&cmwkup->divm2dpllper);
274 /* Set the PLL to bypass Mode */
275 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
277 while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
280 clksel = clksel & (~CLK_SEL_MASK);
281 clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
282 writel(clksel, &cmwkup->clkseldpllper);
284 div_m2 = div_m2 & ~CLK_DIV2_MASK;
285 div_m2 = div_m2 | PERPLL_M2;
286 writel(div_m2, &cmwkup->divm2dpllper);
288 clkmode = clkmode | CLK_MODE_SEL;
289 writel(clkmode, &cmwkup->clkmoddpllper);
291 while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
295 void ddr_pll_config(unsigned int ddrpll_m)
297 u32 clkmode, clksel, div_m2;
299 clkmode = readl(&cmwkup->clkmoddpllddr);
300 clksel = readl(&cmwkup->clkseldpllddr);
301 div_m2 = readl(&cmwkup->divm2dpllddr);
303 /* Set the PLL to bypass Mode */
304 clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
305 writel(clkmode, &cmwkup->clkmoddpllddr);
307 /* Wait till bypass mode is enabled */
308 while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
312 clksel = clksel & (~CLK_SEL_MASK);
313 clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
314 writel(clksel, &cmwkup->clkseldpllddr);
316 div_m2 = div_m2 & CLK_DIV_SEL;
317 div_m2 = div_m2 | DDRPLL_M2;
318 writel(div_m2, &cmwkup->divm2dpllddr);
320 clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
321 writel(clkmode, &cmwkup->clkmoddpllddr);
323 /* Wait till dpll is locked */
324 while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
328 void enable_emif_clocks(void)
330 /* Enable the EMIF_FW Functional clock */
331 writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
332 /* Enable EMIF0 Clock */
333 writel(PRCM_MOD_EN, &cmper->emifclkctrl);
334 /* Poll if module is functional */
335 while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
340 * Configure the PLL/PRCM for necessary peripherals
348 /* Enable the required interconnect clocks */
349 enable_interface_clocks();
351 /* Power domain wake up transition */
352 power_domain_wkup_transition();
354 /* Enable the required peripherals */