4 * clocks for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/hardware.h>
25 #define PRCM_MOD_EN 0x2
26 #define PRCM_FORCE_WAKEUP 0x2
27 #define PRCM_FUNCTL 0x0
29 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
30 #define PRCM_L3_GCLK_ACTIVITY BIT(4)
32 #define PLL_BYPASS_MODE 0x4
33 #define ST_MN_BYPASS 0x00000100
34 #define ST_DPLL_CLK 0x00000001
35 #define CLK_SEL_MASK 0x7ffff
36 #define CLK_DIV_MASK 0x1f
37 #define CLK_DIV2_MASK 0x7f
38 #define CLK_SEL_SHIFT 0x8
39 #define CLK_MODE_SEL 0x7
40 #define CLK_MODE_MASK 0xfffffff8
41 #define CLK_DIV_SEL 0xFFFFFFE0
42 #define CPGMAC0_IDLE 0x30000
44 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
45 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
46 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
48 static void enable_interface_clocks(void)
50 /* Enable all the Interconnect Modules */
51 writel(PRCM_MOD_EN, &cmper->l3clkctrl);
52 while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
55 writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
56 while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
59 writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
60 while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
63 writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
64 while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
67 writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
68 while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
71 writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
72 while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
75 writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
76 while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
81 * Force power domain wake up transition
82 * Ensure that the corresponding interface clock is active before
83 * using the peripheral
85 static void power_domain_wkup_transition(void)
87 writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
88 writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
89 writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
90 writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
91 writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
95 * Enable the peripheral clock for required peripherals
97 static void enable_per_clocks(void)
99 /* Enable the control module though RBL would have done it*/
100 writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
101 while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
104 /* Enable the module clock */
105 writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
106 while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
109 /* Select the Master osc 24 MHZ as Timer2 clock source */
110 writel(0x1, &cmdpll->clktimer2clk);
113 writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
114 while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
118 writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
119 while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
123 writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
124 while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
128 writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
129 while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
133 writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
134 while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
138 writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
139 while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
143 writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
144 while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
148 writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
149 while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
153 static void mpu_pll_config(void)
155 u32 clkmode, clksel, div_m2;
157 clkmode = readl(&cmwkup->clkmoddpllmpu);
158 clksel = readl(&cmwkup->clkseldpllmpu);
159 div_m2 = readl(&cmwkup->divm2dpllmpu);
161 /* Set the PLL to bypass Mode */
162 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
163 while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
166 clksel = clksel & (~CLK_SEL_MASK);
167 clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
168 writel(clksel, &cmwkup->clkseldpllmpu);
170 div_m2 = div_m2 & ~CLK_DIV_MASK;
171 div_m2 = div_m2 | MPUPLL_M2;
172 writel(div_m2, &cmwkup->divm2dpllmpu);
174 clkmode = clkmode | CLK_MODE_SEL;
175 writel(clkmode, &cmwkup->clkmoddpllmpu);
177 while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
181 static void core_pll_config(void)
183 u32 clkmode, clksel, div_m4, div_m5, div_m6;
185 clkmode = readl(&cmwkup->clkmoddpllcore);
186 clksel = readl(&cmwkup->clkseldpllcore);
187 div_m4 = readl(&cmwkup->divm4dpllcore);
188 div_m5 = readl(&cmwkup->divm5dpllcore);
189 div_m6 = readl(&cmwkup->divm6dpllcore);
191 /* Set the PLL to bypass Mode */
192 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
194 while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
197 clksel = clksel & (~CLK_SEL_MASK);
198 clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
199 writel(clksel, &cmwkup->clkseldpllcore);
201 div_m4 = div_m4 & ~CLK_DIV_MASK;
202 div_m4 = div_m4 | COREPLL_M4;
203 writel(div_m4, &cmwkup->divm4dpllcore);
205 div_m5 = div_m5 & ~CLK_DIV_MASK;
206 div_m5 = div_m5 | COREPLL_M5;
207 writel(div_m5, &cmwkup->divm5dpllcore);
209 div_m6 = div_m6 & ~CLK_DIV_MASK;
210 div_m6 = div_m6 | COREPLL_M6;
211 writel(div_m6, &cmwkup->divm6dpllcore);
213 clkmode = clkmode | CLK_MODE_SEL;
214 writel(clkmode, &cmwkup->clkmoddpllcore);
216 while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
220 static void per_pll_config(void)
222 u32 clkmode, clksel, div_m2;
224 clkmode = readl(&cmwkup->clkmoddpllper);
225 clksel = readl(&cmwkup->clkseldpllper);
226 div_m2 = readl(&cmwkup->divm2dpllper);
228 /* Set the PLL to bypass Mode */
229 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
231 while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
234 clksel = clksel & (~CLK_SEL_MASK);
235 clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
236 writel(clksel, &cmwkup->clkseldpllper);
238 div_m2 = div_m2 & ~CLK_DIV2_MASK;
239 div_m2 = div_m2 | PERPLL_M2;
240 writel(div_m2, &cmwkup->divm2dpllper);
242 clkmode = clkmode | CLK_MODE_SEL;
243 writel(clkmode, &cmwkup->clkmoddpllper);
245 while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
249 static void ddr_pll_config(void)
251 u32 clkmode, clksel, div_m2;
253 clkmode = readl(&cmwkup->clkmoddpllddr);
254 clksel = readl(&cmwkup->clkseldpllddr);
255 div_m2 = readl(&cmwkup->divm2dpllddr);
257 /* Set the PLL to bypass Mode */
258 clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
259 writel(clkmode, &cmwkup->clkmoddpllddr);
261 /* Wait till bypass mode is enabled */
262 while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
266 clksel = clksel & (~CLK_SEL_MASK);
267 clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
268 writel(clksel, &cmwkup->clkseldpllddr);
270 div_m2 = div_m2 & CLK_DIV_SEL;
271 div_m2 = div_m2 | DDRPLL_M2;
272 writel(div_m2, &cmwkup->divm2dpllddr);
274 clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
275 writel(clkmode, &cmwkup->clkmoddpllddr);
277 /* Wait till dpll is locked */
278 while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
282 void enable_emif_clocks(void)
284 /* Enable the EMIF_FW Functional clock */
285 writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
286 /* Enable EMIF0 Clock */
287 writel(PRCM_MOD_EN, &cmper->emifclkctrl);
288 /* Poll if module is functional */
289 while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
294 * Configure the PLL/PRCM for necessary peripherals
303 /* Enable the required interconnect clocks */
304 enable_interface_clocks();
306 /* Power domain wake up transition */
307 power_domain_wkup_transition();
309 /* Enable the required peripherals */