4 * clocks for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/hardware.h>
25 #define PRCM_MOD_EN 0x2
26 #define PRCM_FORCE_WAKEUP 0x2
27 #define PRCM_FUNCTL 0x0
29 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
30 #define PRCM_L3_GCLK_ACTIVITY BIT(4)
32 #define PLL_BYPASS_MODE 0x4
33 #define ST_MN_BYPASS 0x00000100
34 #define ST_DPLL_CLK 0x00000001
35 #define CLK_SEL_MASK 0x7ffff
36 #define CLK_DIV_MASK 0x1f
37 #define CLK_DIV2_MASK 0x7f
38 #define CLK_SEL_SHIFT 0x8
39 #define CLK_MODE_SEL 0x7
40 #define CLK_MODE_MASK 0xfffffff8
41 #define CLK_DIV_SEL 0xFFFFFFE0
42 #define CPGMAC0_IDLE 0x30000
44 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
45 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
46 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
47 const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
49 static void enable_interface_clocks(void)
51 /* Enable all the Interconnect Modules */
52 writel(PRCM_MOD_EN, &cmper->l3clkctrl);
53 while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
56 writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
57 while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
60 writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
61 while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
64 writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
65 while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
68 writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
69 while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
72 writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
73 while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
76 writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
77 while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
82 * Force power domain wake up transition
83 * Ensure that the corresponding interface clock is active before
84 * using the peripheral
86 static void power_domain_wkup_transition(void)
88 writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
89 writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
90 writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
91 writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
92 writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
96 * Enable the peripheral clock for required peripherals
98 static void enable_per_clocks(void)
100 /* Enable the control module though RBL would have done it*/
101 writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
102 while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
105 /* Enable the module clock */
106 writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
107 while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
110 /* Select the Master osc 24 MHZ as Timer2 clock source */
111 writel(0x1, &cmdpll->clktimer2clk);
114 writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
115 while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
119 #ifdef CONFIG_SERIAL2
120 writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
121 while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
123 #endif /* CONFIG_SERIAL2 */
126 #ifdef CONFIG_SERIAL3
127 writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
128 while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
130 #endif /* CONFIG_SERIAL3 */
133 #ifdef CONFIG_SERIAL4
134 writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
135 while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
137 #endif /* CONFIG_SERIAL4 */
140 #ifdef CONFIG_SERIAL5
141 writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
142 while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
144 #endif /* CONFIG_SERIAL5 */
147 #ifdef CONFIG_SERIAL6
148 writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
149 while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
151 #endif /* CONFIG_SERIAL6 */
154 writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
155 while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
159 writel(PRCM_MOD_EN, &cmper->elmclkctrl);
160 while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
164 writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
165 while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
169 writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
170 while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
174 writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
175 while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
179 writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
180 while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
184 writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
185 while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
189 writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
190 while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
194 writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
195 while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
199 writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
200 while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
204 writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
205 while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
209 static void mpu_pll_config(void)
211 u32 clkmode, clksel, div_m2;
213 clkmode = readl(&cmwkup->clkmoddpllmpu);
214 clksel = readl(&cmwkup->clkseldpllmpu);
215 div_m2 = readl(&cmwkup->divm2dpllmpu);
217 /* Set the PLL to bypass Mode */
218 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
219 while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
222 clksel = clksel & (~CLK_SEL_MASK);
223 clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
224 writel(clksel, &cmwkup->clkseldpllmpu);
226 div_m2 = div_m2 & ~CLK_DIV_MASK;
227 div_m2 = div_m2 | MPUPLL_M2;
228 writel(div_m2, &cmwkup->divm2dpllmpu);
230 clkmode = clkmode | CLK_MODE_SEL;
231 writel(clkmode, &cmwkup->clkmoddpllmpu);
233 while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
237 static void core_pll_config(void)
239 u32 clkmode, clksel, div_m4, div_m5, div_m6;
241 clkmode = readl(&cmwkup->clkmoddpllcore);
242 clksel = readl(&cmwkup->clkseldpllcore);
243 div_m4 = readl(&cmwkup->divm4dpllcore);
244 div_m5 = readl(&cmwkup->divm5dpllcore);
245 div_m6 = readl(&cmwkup->divm6dpllcore);
247 /* Set the PLL to bypass Mode */
248 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
250 while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
253 clksel = clksel & (~CLK_SEL_MASK);
254 clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
255 writel(clksel, &cmwkup->clkseldpllcore);
257 div_m4 = div_m4 & ~CLK_DIV_MASK;
258 div_m4 = div_m4 | COREPLL_M4;
259 writel(div_m4, &cmwkup->divm4dpllcore);
261 div_m5 = div_m5 & ~CLK_DIV_MASK;
262 div_m5 = div_m5 | COREPLL_M5;
263 writel(div_m5, &cmwkup->divm5dpllcore);
265 div_m6 = div_m6 & ~CLK_DIV_MASK;
266 div_m6 = div_m6 | COREPLL_M6;
267 writel(div_m6, &cmwkup->divm6dpllcore);
269 clkmode = clkmode | CLK_MODE_SEL;
270 writel(clkmode, &cmwkup->clkmoddpllcore);
272 while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
276 static void per_pll_config(void)
278 u32 clkmode, clksel, div_m2;
280 clkmode = readl(&cmwkup->clkmoddpllper);
281 clksel = readl(&cmwkup->clkseldpllper);
282 div_m2 = readl(&cmwkup->divm2dpllper);
284 /* Set the PLL to bypass Mode */
285 writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
287 while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
290 clksel = clksel & (~CLK_SEL_MASK);
291 clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
292 writel(clksel, &cmwkup->clkseldpllper);
294 div_m2 = div_m2 & ~CLK_DIV2_MASK;
295 div_m2 = div_m2 | PERPLL_M2;
296 writel(div_m2, &cmwkup->divm2dpllper);
298 clkmode = clkmode | CLK_MODE_SEL;
299 writel(clkmode, &cmwkup->clkmoddpllper);
301 while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
305 void ddr_pll_config(unsigned int ddrpll_m)
307 u32 clkmode, clksel, div_m2;
309 clkmode = readl(&cmwkup->clkmoddpllddr);
310 clksel = readl(&cmwkup->clkseldpllddr);
311 div_m2 = readl(&cmwkup->divm2dpllddr);
313 /* Set the PLL to bypass Mode */
314 clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
315 writel(clkmode, &cmwkup->clkmoddpllddr);
317 /* Wait till bypass mode is enabled */
318 while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
322 clksel = clksel & (~CLK_SEL_MASK);
323 clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
324 writel(clksel, &cmwkup->clkseldpllddr);
326 div_m2 = div_m2 & CLK_DIV_SEL;
327 div_m2 = div_m2 | DDRPLL_M2;
328 writel(div_m2, &cmwkup->divm2dpllddr);
330 clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
331 writel(clkmode, &cmwkup->clkmoddpllddr);
333 /* Wait till dpll is locked */
334 while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
338 void enable_emif_clocks(void)
340 /* Enable the EMIF_FW Functional clock */
341 writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
342 /* Enable EMIF0 Clock */
343 writel(PRCM_MOD_EN, &cmper->emifclkctrl);
344 /* Poll if module is functional */
345 while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
350 * Configure the PLL/PRCM for necessary peripherals
358 /* Enable the required interconnect clocks */
359 enable_interface_clocks();
361 /* Power domain wake up transition */
362 power_domain_wkup_transition();
364 /* Enable the required peripherals */