arch/arm/cpu/armv7/am33xx/clock.c

   1 /*
   2  * clock.c
   3  *
   4  * clocks for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/io.h>
  24
  25 #define PRCM_MOD_EN             0x2
  26 #define PRCM_FORCE_WAKEUP       0x2
  27 #define PRCM_FUNCTL             0x0
  28
  29 #define PRCM_EMIF_CLK_ACTIVITY  BIT(2)
  30 #define PRCM_L3_GCLK_ACTIVITY   BIT(4)
  31
  32 #define PLL_BYPASS_MODE         0x4
  33 #define ST_MN_BYPASS            0x00000100
  34 #define ST_DPLL_CLK             0x00000001
  35 #define CLK_SEL_MASK            0x7ffff
  36 #define CLK_DIV_MASK            0x1f
  37 #define CLK_DIV2_MASK           0x7f
  38 #define CLK_SEL_SHIFT           0x8
  39 #define CLK_MODE_SEL            0x7
  40 #define CLK_MODE_MASK           0xfffffff8
  41 #define CLK_DIV_SEL             0xFFFFFFE0
  42 #define CPGMAC0_IDLE            0x30000
  43
  44 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  45 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  46 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  47 const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
  48
  49 static void enable_interface_clocks(void)
  50 {
  51         /* Enable all the Interconnect Modules */
  52         writel(PRCM_MOD_EN, &cmper->l3clkctrl);
  53         while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
  54                 ;
  55
  56         writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
  57         while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
  58                 ;
  59
  60         writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
  61         while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
  62                 ;
  63
  64         writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
  65         while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
  66                 ;
  67
  68         writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
  69         while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
  70                 ;
  71
  72         writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
  73         while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
  74                 ;
  75
  76         writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
  77         while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
  78                 ;
  79 }
  80
  81 /*
  82  * Force power domain wake up transition
  83  * Ensure that the corresponding interface clock is active before
  84  * using the peripheral
  85  */
  86 static void power_domain_wkup_transition(void)
  87 {
  88         writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
  89         writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
  90         writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
  91         writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
  92         writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
  93 }
  94
  95 /*
  96  * Enable the peripheral clock for required peripherals
  97  */
  98 static void enable_per_clocks(void)
  99 {
 100         /* Enable the control module though RBL would have done it*/
 101         writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
 102         while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
 103                 ;
 104
 105         /* Enable the module clock */
 106         writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
 107         while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 108                 ;
 109
 110         /* Select the Master osc 24 MHZ as Timer2 clock source */
 111         writel(0x1, &cmdpll->clktimer2clk);
 112
 113         /* UART0 */
 114         writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 115         while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 116                 ;
 117
 118         /* MMC0*/
 119         writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 120         while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
 121                 ;
 122
 123         /* i2c0 */
 124         writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
 125         while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
 126                 ;
 127
 128         /* gpio1 module */
 129         writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
 130         while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
 131                 ;
 132
 133         /* gpio2 module */
 134         writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
 135         while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
 136                 ;
 137
 138         /* gpio3 module */
 139         writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
 140         while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
 141                 ;
 142
 143         /* i2c1 */
 144         writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
 145         while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
 146                 ;
 147
 148         /* Ethernet */
 149         writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
 150         while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
 151                 ;
 152
 153         /* spi0 */
 154         writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
 155         while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
 156                 ;
 157
 158         /* RTC */
 159         writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
 160         while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
 161                 ;
 162 }
 163
 164 static void mpu_pll_config(void)
 165 {
 166         u32 clkmode, clksel, div_m2;
 167
 168         clkmode = readl(&cmwkup->clkmoddpllmpu);
 169         clksel = readl(&cmwkup->clkseldpllmpu);
 170         div_m2 = readl(&cmwkup->divm2dpllmpu);
 171
 172         /* Set the PLL to bypass Mode */
 173         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 174         while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
 175                 ;
 176
 177         clksel = clksel & (~CLK_SEL_MASK);
 178         clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
 179         writel(clksel, &cmwkup->clkseldpllmpu);
 180
 181         div_m2 = div_m2 & ~CLK_DIV_MASK;
 182         div_m2 = div_m2 | MPUPLL_M2;
 183         writel(div_m2, &cmwkup->divm2dpllmpu);
 184
 185         clkmode = clkmode | CLK_MODE_SEL;
 186         writel(clkmode, &cmwkup->clkmoddpllmpu);
 187
 188         while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
 189                 ;
 190 }
 191
 192 static void core_pll_config(void)
 193 {
 194         u32 clkmode, clksel, div_m4, div_m5, div_m6;
 195
 196         clkmode = readl(&cmwkup->clkmoddpllcore);
 197         clksel = readl(&cmwkup->clkseldpllcore);
 198         div_m4 = readl(&cmwkup->divm4dpllcore);
 199         div_m5 = readl(&cmwkup->divm5dpllcore);
 200         div_m6 = readl(&cmwkup->divm6dpllcore);
 201
 202         /* Set the PLL to bypass Mode */
 203         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
 204
 205         while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
 206                 ;
 207
 208         clksel = clksel & (~CLK_SEL_MASK);
 209         clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
 210         writel(clksel, &cmwkup->clkseldpllcore);
 211
 212         div_m4 = div_m4 & ~CLK_DIV_MASK;
 213         div_m4 = div_m4 | COREPLL_M4;
 214         writel(div_m4, &cmwkup->divm4dpllcore);
 215
 216         div_m5 = div_m5 & ~CLK_DIV_MASK;
 217         div_m5 = div_m5 | COREPLL_M5;
 218         writel(div_m5, &cmwkup->divm5dpllcore);
 219
 220         div_m6 = div_m6 & ~CLK_DIV_MASK;
 221         div_m6 = div_m6 | COREPLL_M6;
 222         writel(div_m6, &cmwkup->divm6dpllcore);
 223
 224         clkmode = clkmode | CLK_MODE_SEL;
 225         writel(clkmode, &cmwkup->clkmoddpllcore);
 226
 227         while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
 228                 ;
 229 }
 230
 231 static void per_pll_config(void)
 232 {
 233         u32 clkmode, clksel, div_m2;
 234
 235         clkmode = readl(&cmwkup->clkmoddpllper);
 236         clksel = readl(&cmwkup->clkseldpllper);
 237         div_m2 = readl(&cmwkup->divm2dpllper);
 238
 239         /* Set the PLL to bypass Mode */
 240         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
 241
 242         while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
 243                 ;
 244
 245         clksel = clksel & (~CLK_SEL_MASK);
 246         clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
 247         writel(clksel, &cmwkup->clkseldpllper);
 248
 249         div_m2 = div_m2 & ~CLK_DIV2_MASK;
 250         div_m2 = div_m2 | PERPLL_M2;
 251         writel(div_m2, &cmwkup->divm2dpllper);
 252
 253         clkmode = clkmode | CLK_MODE_SEL;
 254         writel(clkmode, &cmwkup->clkmoddpllper);
 255
 256         while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 257                 ;
 258 }
 259
 260 void ddr_pll_config(unsigned int ddrpll_m)
 261 {
 262         u32 clkmode, clksel, div_m2;
 263
 264         clkmode = readl(&cmwkup->clkmoddpllddr);
 265         clksel = readl(&cmwkup->clkseldpllddr);
 266         div_m2 = readl(&cmwkup->divm2dpllddr);
 267
 268         /* Set the PLL to bypass Mode */
 269         clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
 270         writel(clkmode, &cmwkup->clkmoddpllddr);
 271
 272         /* Wait till bypass mode is enabled */
 273         while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
 274                                 != ST_MN_BYPASS)
 275                 ;
 276
 277         clksel = clksel & (~CLK_SEL_MASK);
 278         clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
 279         writel(clksel, &cmwkup->clkseldpllddr);
 280
 281         div_m2 = div_m2 & CLK_DIV_SEL;
 282         div_m2 = div_m2 | DDRPLL_M2;
 283         writel(div_m2, &cmwkup->divm2dpllddr);
 284
 285         clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
 286         writel(clkmode, &cmwkup->clkmoddpllddr);
 287
 288         /* Wait till dpll is locked */
 289         while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
 290                 ;
 291 }
 292
 293 void enable_emif_clocks(void)
 294 {
 295         /* Enable the  EMIF_FW Functional clock */
 296         writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 297         /* Enable EMIF0 Clock */
 298         writel(PRCM_MOD_EN, &cmper->emifclkctrl);
 299         /* Poll if module is functional */
 300         while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 301                 ;
 302 }
 303
 304 /*
 305  * Configure the PLL/PRCM for necessary peripherals
 306  */
 307 void pll_init()
 308 {
 309         mpu_pll_config();
 310         core_pll_config();
 311         per_pll_config();
 312
 313         /* Enable the required interconnect clocks */
 314         enable_interface_clocks();
 315
 316         /* Power domain wake up transition */
 317         power_domain_wkup_transition();
 318
 319         /* Enable the required peripherals */
 320         enable_per_clocks();
 321 }