arch/arm/cpu/armv7/am33xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Common board functions for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <asm/arch/cpu.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/omap.h>
  24 #include <asm/arch/ddr_defs.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/mmc_host_def.h>
  28 #include <asm/arch/common_def.h>
  29 #include <asm/io.h>
  30 #include <asm/omap_common.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  40 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
  41 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  42
  43 static const struct gpio_bank gpio_bank_am33xx[4] = {
  44         { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
  45         { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
  46         { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
  47         { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
  48 };
  49
  50 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  51
  52 /* MII mode defines */
  53 #define MII_MODE_ENABLE         0x0
  54 #define RGMII_MODE_ENABLE       0xA
  55
  56 /* GPIO that controls power to DDR on EVM-SK */
  57 #define GPIO_DDR_VTT_EN         7
  58
  59 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  60
  61 #define NO_OF_MAC_ADDR          3
  62 #define ETH_ALEN                6
  63 #define NAME_LEN                8
  64
  65 struct am335x_baseboard_id {
  66         unsigned int  magic;
  67         char name[NAME_LEN];
  68         char version[4];
  69         char serial[12];
  70         char config[32];
  71         char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
  72 };
  73
  74 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
  75
  76 static inline int board_is_bone(void)
  77 {
  78         return !strncmp(header.name, "A335BONE", NAME_LEN);
  79 }
  80
  81 static inline int board_is_evm_sk(void)
  82 {
  83         return !strncmp("A335X_SK", header.name, NAME_LEN);
  84 }
  85
  86 /*
  87  * Read header information from EEPROM into global structure.
  88  */
  89 static int read_eeprom(void)
  90 {
  91         /* Check if baseboard eeprom is available */
  92         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  93                 puts("Could not probe the EEPROM; something fundamentally "
  94                         "wrong on the I2C bus.\n");
  95                 return -ENODEV;
  96         }
  97
  98         /* read the eeprom using i2c */
  99         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
 100                                                         sizeof(header))) {
 101                 puts("Could not read the EEPROM; something fundamentally"
 102                         " wrong on the I2C bus.\n");
 103                 return -EIO;
 104         }
 105
 106         if (header.magic != 0xEE3355AA) {
 107                 /*
 108                  * read the eeprom using i2c again,
 109                  * but use only a 1 byte address
 110                  */
 111                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
 112                                         (uchar *)&header, sizeof(header))) {
 113                         puts("Could not read the EEPROM; something "
 114                                 "fundamentally wrong on the I2C bus.\n");
 115                         return -EIO;
 116                 }
 117
 118                 if (header.magic != 0xEE3355AA) {
 119                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 120                                         header.magic);
 121                         return -EINVAL;
 122                 }
 123         }
 124
 125         return 0;
 126 }
 127
 128 /* UART Defines */
 129 #ifdef CONFIG_SPL_BUILD
 130 #define UART_RESET              (0x1 << 1)
 131 #define UART_CLK_RUNNING_MASK   0x1
 132 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 133 #endif
 134
 135 #ifdef CONFIG_SPL_BUILD
 136 /* Initialize timer */
 137 static void init_timer(void)
 138 {
 139         /* Reset the Timer */
 140         writel(0x2, (&timer_base->tscir));
 141
 142         /* Wait until the reset is done */
 143         while (readl(&timer_base->tiocp_cfg) & 1)
 144                 ;
 145
 146         /* Start the Timer */
 147         writel(0x1, (&timer_base->tclr));
 148 }
 149 #endif
 150
 151 /*
 152  * Determine what type of DDR we have.
 153  */
 154 static short inline board_memory_type(void)
 155 {
 156         /* The following boards are known to use DDR3. */
 157         if (board_is_evm_sk())
 158                 return EMIF_REG_SDRAM_TYPE_DDR3;
 159
 160         return EMIF_REG_SDRAM_TYPE_DDR2;
 161 }
 162
 163 /*
 164  * early system init of muxing and clocks.
 165  */
 166 void s_init(void)
 167 {
 168         /* WDT1 is already running when the bootloader gets control
 169          * Disable it to avoid "random" resets
 170          */
 171         writel(0xAAAA, &wdtimer->wdtwspr);
 172         while (readl(&wdtimer->wdtwwps) != 0x0)
 173                 ;
 174         writel(0x5555, &wdtimer->wdtwspr);
 175         while (readl(&wdtimer->wdtwwps) != 0x0)
 176                 ;
 177
 178 #ifdef CONFIG_SPL_BUILD
 179         /* Setup the PLLs and the clocks for the peripherals */
 180         pll_init();
 181
 182         /* UART softreset */
 183         u32 regVal;
 184
 185         enable_uart0_pin_mux();
 186
 187         regVal = readl(&uart_base->uartsyscfg);
 188         regVal |= UART_RESET;
 189         writel(regVal, &uart_base->uartsyscfg);
 190         while ((readl(&uart_base->uartsyssts) &
 191                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 192                 ;
 193
 194         /* Disable smart idle */
 195         regVal = readl(&uart_base->uartsyscfg);
 196         regVal |= UART_SMART_IDLE_EN;
 197         writel(regVal, &uart_base->uartsyscfg);
 198
 199         /* Initialize the Timer */
 200         init_timer();
 201
 202         preloader_console_init();
 203
 204         /* Initalize the board header */
 205         enable_i2c0_pin_mux();
 206         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 207         if (read_eeprom() < 0)
 208                 puts("Could not get board ID.\n");
 209
 210         if (board_is_evm_sk()) {
 211                 /*
 212                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 213                  * This is safe enough to do on older revs.
 214                  */
 215                 enable_gpio0_7_pin_mux();
 216                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 217                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 218         }
 219
 220         config_ddr(board_memory_type());
 221 #endif
 222
 223         /* Enable MMC0 */
 224         enable_mmc0_pin_mux();
 225 }
 226
 227 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 228 int board_mmc_init(bd_t *bis)
 229 {
 230         return omap_mmc_init(0, 0, 0);
 231 }
 232 #endif
 233
 234 void setup_clocks_for_console(void)
 235 {
 236         /* Not yet implemented */
 237         return;
 238 }
 239
 240 /*
 241  * Basic board specific setup
 242  */
 243 int board_init(void)
 244 {
 245         enable_uart0_pin_mux();
 246
 247         enable_i2c0_pin_mux();
 248         enable_i2c1_pin_mux();
 249         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 250         if (read_eeprom() < 0)
 251                 puts("Could not get board ID.\n");
 252
 253         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 254
 255         return 0;
 256 }
 257
 258 #ifdef CONFIG_DRIVER_TI_CPSW
 259 static void cpsw_control(int enabled)
 260 {
 261         /* VTP can be added here */
 262
 263         return;
 264 }
 265
 266 static struct cpsw_slave_data cpsw_slaves[] = {
 267         {
 268                 .slave_reg_ofs  = 0x208,
 269                 .sliver_reg_ofs = 0xd80,
 270                 .phy_id         = 0,
 271         },
 272         {
 273                 .slave_reg_ofs  = 0x308,
 274                 .sliver_reg_ofs = 0xdc0,
 275                 .phy_id         = 1,
 276         },
 277 };
 278
 279 static struct cpsw_platform_data cpsw_data = {
 280         .mdio_base              = AM335X_CPSW_MDIO_BASE,
 281         .cpsw_base              = AM335X_CPSW_BASE,
 282         .mdio_div               = 0xff,
 283         .channels               = 8,
 284         .cpdma_reg_ofs          = 0x800,
 285         .slaves                 = 1,
 286         .slave_data             = cpsw_slaves,
 287         .ale_reg_ofs            = 0xd00,
 288         .ale_entries            = 1024,
 289         .host_port_reg_ofs      = 0x108,
 290         .hw_stats_reg_ofs       = 0x900,
 291         .mac_control            = (1 << 5),
 292         .control                = cpsw_control,
 293         .host_port_num          = 0,
 294         .version                = CPSW_CTRL_VERSION_2,
 295 };
 296
 297 int board_eth_init(bd_t *bis)
 298 {
 299         uint8_t mac_addr[6];
 300         uint32_t mac_hi, mac_lo;
 301
 302         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 303                 debug("<ethaddr> not set. Reading from E-fuse\n");
 304                 /* try reading mac address from efuse */
 305                 mac_lo = readl(&cdev->macid0l);
 306                 mac_hi = readl(&cdev->macid0h);
 307                 mac_addr[0] = mac_hi & 0xFF;
 308                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 309                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 310                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 311                 mac_addr[4] = mac_lo & 0xFF;
 312                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 313
 314                 if (is_valid_ether_addr(mac_addr))
 315                         eth_setenv_enetaddr("ethaddr", mac_addr);
 316                 else
 317                         return -1;
 318         }
 319
 320         if (board_is_bone()) {
 321                 enable_mii1_pin_mux();
 322                 writel(MII_MODE_ENABLE, &cdev->miisel);
 323                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 324                                 PHY_INTERFACE_MODE_MII;
 325         } else {
 326                 enable_rgmii1_pin_mux();
 327                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 328                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 329                                 PHY_INTERFACE_MODE_RGMII;
 330         }
 331
 332         return cpsw_register(&cpsw_data);
 333 }
 334 #endif