arch/arm/cpu/armv7/am33xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Common board functions for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <asm/arch/cpu.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/omap.h>
  24 #include <asm/arch/ddr_defs.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/mmc_host_def.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/io.h>
  30 #include <asm/omap_common.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  40 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
  41 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  42
  43 static const struct gpio_bank gpio_bank_am33xx[4] = {
  44         { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
  45         { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
  46         { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
  47         { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
  48 };
  49
  50 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  51
  52 /* MII mode defines */
  53 #define MII_MODE_ENABLE         0x0
  54 #define RGMII_MODE_ENABLE       0xA
  55
  56 /* GPIO that controls power to DDR on EVM-SK */
  57 #define GPIO_DDR_VTT_EN         7
  58
  59 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  60
  61 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
  62
  63 static inline int board_is_bone(void)
  64 {
  65         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
  66 }
  67
  68 static inline int board_is_evm_sk(void)
  69 {
  70         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
  71 }
  72
  73 /*
  74  * Read header information from EEPROM into global structure.
  75  */
  76 static int read_eeprom(void)
  77 {
  78         /* Check if baseboard eeprom is available */
  79         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  80                 puts("Could not probe the EEPROM; something fundamentally "
  81                         "wrong on the I2C bus.\n");
  82                 return -ENODEV;
  83         }
  84
  85         /* read the eeprom using i2c */
  86         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  87                                                         sizeof(header))) {
  88                 puts("Could not read the EEPROM; something fundamentally"
  89                         " wrong on the I2C bus.\n");
  90                 return -EIO;
  91         }
  92
  93         if (header.magic != 0xEE3355AA) {
  94                 /*
  95                  * read the eeprom using i2c again,
  96                  * but use only a 1 byte address
  97                  */
  98                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
  99                                         (uchar *)&header, sizeof(header))) {
 100                         puts("Could not read the EEPROM; something "
 101                                 "fundamentally wrong on the I2C bus.\n");
 102                         return -EIO;
 103                 }
 104
 105                 if (header.magic != 0xEE3355AA) {
 106                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 107                                         header.magic);
 108                         return -EINVAL;
 109                 }
 110         }
 111
 112         return 0;
 113 }
 114
 115 /* UART Defines */
 116 #ifdef CONFIG_SPL_BUILD
 117 #define UART_RESET              (0x1 << 1)
 118 #define UART_CLK_RUNNING_MASK   0x1
 119 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 120 #endif
 121
 122 #ifdef CONFIG_SPL_BUILD
 123 /* Initialize timer */
 124 static void init_timer(void)
 125 {
 126         /* Reset the Timer */
 127         writel(0x2, (&timer_base->tscir));
 128
 129         /* Wait until the reset is done */
 130         while (readl(&timer_base->tiocp_cfg) & 1)
 131                 ;
 132
 133         /* Start the Timer */
 134         writel(0x1, (&timer_base->tclr));
 135 }
 136 #endif
 137
 138 /*
 139  * Determine what type of DDR we have.
 140  */
 141 static short inline board_memory_type(void)
 142 {
 143         /* The following boards are known to use DDR3. */
 144         if (board_is_evm_sk())
 145                 return EMIF_REG_SDRAM_TYPE_DDR3;
 146
 147         return EMIF_REG_SDRAM_TYPE_DDR2;
 148 }
 149
 150 /*
 151  * early system init of muxing and clocks.
 152  */
 153 void s_init(void)
 154 {
 155         /* WDT1 is already running when the bootloader gets control
 156          * Disable it to avoid "random" resets
 157          */
 158         writel(0xAAAA, &wdtimer->wdtwspr);
 159         while (readl(&wdtimer->wdtwwps) != 0x0)
 160                 ;
 161         writel(0x5555, &wdtimer->wdtwspr);
 162         while (readl(&wdtimer->wdtwwps) != 0x0)
 163                 ;
 164
 165 #ifdef CONFIG_SPL_BUILD
 166         /* Setup the PLLs and the clocks for the peripherals */
 167         pll_init();
 168
 169         /* UART softreset */
 170         u32 regVal;
 171
 172         enable_uart0_pin_mux();
 173
 174         regVal = readl(&uart_base->uartsyscfg);
 175         regVal |= UART_RESET;
 176         writel(regVal, &uart_base->uartsyscfg);
 177         while ((readl(&uart_base->uartsyssts) &
 178                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 179                 ;
 180
 181         /* Disable smart idle */
 182         regVal = readl(&uart_base->uartsyscfg);
 183         regVal |= UART_SMART_IDLE_EN;
 184         writel(regVal, &uart_base->uartsyscfg);
 185
 186         /* Initialize the Timer */
 187         init_timer();
 188
 189         preloader_console_init();
 190
 191         /* Initalize the board header */
 192         enable_i2c0_pin_mux();
 193         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 194         if (read_eeprom() < 0)
 195                 puts("Could not get board ID.\n");
 196
 197         enable_board_pin_mux(&header);
 198         if (board_is_evm_sk()) {
 199                 /*
 200                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 201                  * This is safe enough to do on older revs.
 202                  */
 203                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 204                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 205         }
 206
 207         config_ddr(board_memory_type());
 208 #endif
 209 }
 210
 211 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 212 int board_mmc_init(bd_t *bis)
 213 {
 214         int ret;
 215
 216         ret = omap_mmc_init(0, 0, 0);
 217         if (ret)
 218                 return ret;
 219
 220         return omap_mmc_init(1, 0, 0);
 221 }
 222 #endif
 223
 224 void setup_clocks_for_console(void)
 225 {
 226         /* Not yet implemented */
 227         return;
 228 }
 229
 230 /*
 231  * Basic board specific setup.  Pinmux has been handled already.
 232  */
 233 int board_init(void)
 234 {
 235         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 236         if (read_eeprom() < 0)
 237                 puts("Could not get board ID.\n");
 238
 239         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 240
 241         return 0;
 242 }
 243
 244 #ifdef CONFIG_DRIVER_TI_CPSW
 245 static void cpsw_control(int enabled)
 246 {
 247         /* VTP can be added here */
 248
 249         return;
 250 }
 251
 252 static struct cpsw_slave_data cpsw_slaves[] = {
 253         {
 254                 .slave_reg_ofs  = 0x208,
 255                 .sliver_reg_ofs = 0xd80,
 256                 .phy_id         = 0,
 257         },
 258         {
 259                 .slave_reg_ofs  = 0x308,
 260                 .sliver_reg_ofs = 0xdc0,
 261                 .phy_id         = 1,
 262         },
 263 };
 264
 265 static struct cpsw_platform_data cpsw_data = {
 266         .mdio_base              = AM335X_CPSW_MDIO_BASE,
 267         .cpsw_base              = AM335X_CPSW_BASE,
 268         .mdio_div               = 0xff,
 269         .channels               = 8,
 270         .cpdma_reg_ofs          = 0x800,
 271         .slaves                 = 1,
 272         .slave_data             = cpsw_slaves,
 273         .ale_reg_ofs            = 0xd00,
 274         .ale_entries            = 1024,
 275         .host_port_reg_ofs      = 0x108,
 276         .hw_stats_reg_ofs       = 0x900,
 277         .mac_control            = (1 << 5),
 278         .control                = cpsw_control,
 279         .host_port_num          = 0,
 280         .version                = CPSW_CTRL_VERSION_2,
 281 };
 282
 283 int board_eth_init(bd_t *bis)
 284 {
 285         uint8_t mac_addr[6];
 286         uint32_t mac_hi, mac_lo;
 287
 288         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 289                 debug("<ethaddr> not set. Reading from E-fuse\n");
 290                 /* try reading mac address from efuse */
 291                 mac_lo = readl(&cdev->macid0l);
 292                 mac_hi = readl(&cdev->macid0h);
 293                 mac_addr[0] = mac_hi & 0xFF;
 294                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 295                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 296                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 297                 mac_addr[4] = mac_lo & 0xFF;
 298                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 299
 300                 if (is_valid_ether_addr(mac_addr))
 301                         eth_setenv_enetaddr("ethaddr", mac_addr);
 302                 else
 303                         return -1;
 304         }
 305
 306         if (board_is_bone()) {
 307                 writel(MII_MODE_ENABLE, &cdev->miisel);
 308                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 309                                 PHY_INTERFACE_MODE_MII;
 310         } else {
 311                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 312                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 313                                 PHY_INTERFACE_MODE_RGMII;
 314         }
 315
 316         return cpsw_register(&cpsw_data);
 317 }
 318 #endif