4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h>
31 #include <asm/errno.h>
32 #include <linux/compiler.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/musb.h>
36 #include <asm/omap_musb.h>
37 #include <asm/davinci_rtc.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 static const struct omap_gpio_platdata am33xx_gpio[] = {
43 { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
44 { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
45 { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
46 { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
48 { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
49 { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
53 U_BOOT_DEVICES(am33xx_gpios) = {
54 { "gpio_omap", &am33xx_gpio[0] },
55 { "gpio_omap", &am33xx_gpio[1] },
56 { "gpio_omap", &am33xx_gpio[2] },
57 { "gpio_omap", &am33xx_gpio[3] },
59 { "gpio_omap", &am33xx_gpio[4] },
60 { "gpio_omap", &am33xx_gpio[5] },
64 # ifndef CONFIG_OF_CONTROL
66 * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
67 * the CONFIGs. At the same time, we should move this to the board files.
69 static const struct ns16550_platdata am33xx_serial[] = {
70 { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
71 # ifdef CONFIG_SYS_NS16550_COM2
72 { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
73 # ifdef CONFIG_SYS_NS16550_COM3
74 { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
75 { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
76 { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
77 { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
82 U_BOOT_DEVICES(am33xx_uarts) = {
83 { "serial_omap", &am33xx_serial[0] },
84 # ifdef CONFIG_SYS_NS16550_COM2
85 { "serial_omap", &am33xx_serial[1] },
86 # ifdef CONFIG_SYS_NS16550_COM3
87 { "serial_omap", &am33xx_serial[2] },
88 { "serial_omap", &am33xx_serial[3] },
89 { "serial_omap", &am33xx_serial[4] },
90 { "serial_omap", &am33xx_serial[5] },
98 static const struct gpio_bank gpio_bank_am33xx[] = {
99 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
100 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
101 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
102 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
104 { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
105 { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
109 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
113 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
114 int cpu_mmc_init(bd_t *bis)
118 ret = omap_mmc_init(0, 0, 0, -1, -1);
122 return omap_mmc_init(1, 0, 0, -1, -1);
126 /* AM33XX has two MUSB controllers which can be host or gadget */
127 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
128 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
129 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
131 /* USB 2.0 PHY Control */
132 #define CM_PHY_PWRDN (1 << 0)
133 #define CM_PHY_OTG_PWRDN (1 << 1)
134 #define OTGVDET_EN (1 << 19)
135 #define OTGSESSENDEN (1 << 20)
137 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
140 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
141 OTGVDET_EN | OTGSESSENDEN);
143 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
147 static struct musb_hdrc_config musb_config = {
154 #ifdef CONFIG_AM335X_USB0
155 static void am33xx_otg0_set_phy_power(u8 on)
157 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
160 struct omap_musb_board_data otg0_board_data = {
161 .set_phy_power = am33xx_otg0_set_phy_power,
164 static struct musb_hdrc_platform_data otg0_plat = {
165 .mode = CONFIG_AM335X_USB0_MODE,
166 .config = &musb_config,
168 .platform_ops = &musb_dsps_ops,
169 .board_data = &otg0_board_data,
173 #ifdef CONFIG_AM335X_USB1
174 static void am33xx_otg1_set_phy_power(u8 on)
176 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
179 struct omap_musb_board_data otg1_board_data = {
180 .set_phy_power = am33xx_otg1_set_phy_power,
183 static struct musb_hdrc_platform_data otg1_plat = {
184 .mode = CONFIG_AM335X_USB1_MODE,
185 .config = &musb_config,
187 .platform_ops = &musb_dsps_ops,
188 .board_data = &otg1_board_data,
193 int arch_misc_init(void)
195 #ifdef CONFIG_AM335X_USB0
196 musb_register(&otg0_plat, &otg0_board_data,
197 (void *)USB0_OTG_BASE);
199 #ifdef CONFIG_AM335X_USB1
200 musb_register(&otg1_plat, &otg1_board_data,
201 (void *)USB1_OTG_BASE);
206 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
208 * In the case of non-SPL based booting we'll want to call these
209 * functions a tiny bit later as it will require gd to be set and cleared
210 * and that's not true in s_init in this case so we cannot do it there.
212 int board_early_init_f(void)
221 * This function is the place to do per-board things such as ramp up the
222 * MPU clock frequency.
224 __weak void am33xx_spl_board_init(void)
226 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
227 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
230 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
231 static void rtc32k_enable(void)
233 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
236 * Unlock the RTC's registers. For more details please see the
237 * RTC_SS section of the TRM. In order to unlock we need to
238 * write these specific values (keys) in this order.
240 writel(RTC_KICK0R_WE, &rtc->kick0r);
241 writel(RTC_KICK1R_WE, &rtc->kick1r);
243 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
244 writel((1 << 3) | (1 << 6), &rtc->osc);
248 static void uart_soft_reset(void)
250 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
253 regval = readl(&uart_base->uartsyscfg);
254 regval |= UART_RESET;
255 writel(regval, &uart_base->uartsyscfg);
256 while ((readl(&uart_base->uartsyssts) &
257 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
260 /* Disable smart idle */
261 regval = readl(&uart_base->uartsyscfg);
262 regval |= UART_SMART_IDLE_EN;
263 writel(regval, &uart_base->uartsyscfg);
266 static void watchdog_disable(void)
268 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
270 writel(0xAAAA, &wdtimer->wdtwspr);
271 while (readl(&wdtimer->wdtwwps) != 0x0)
273 writel(0x5555, &wdtimer->wdtwspr);
274 while (readl(&wdtimer->wdtwwps) != 0x0)
281 * The ROM will only have set up sufficient pinmux to allow for the
282 * first 4KiB NOR to be read, we must finish doing what we know of
283 * the NOR mux in this space in order to continue.
285 #ifdef CONFIG_NOR_BOOT
286 enable_norboot_pin_mux();
289 * Save the boot parameters passed from romcode.
290 * We cannot delay the saving further than this,
291 * to prevent overwrites.
293 #ifdef CONFIG_SPL_BUILD
294 save_omap_boot_params();
299 setup_clocks_for_console();
301 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
302 gd->baudrate = CONFIG_BAUDRATE;
304 gd->have_console = 1;
305 #elif defined(CONFIG_SPL_BUILD)
307 preloader_console_init();
309 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
310 /* Enable RTC32K clock */
313 #ifdef CONFIG_SPL_BUILD
314 board_early_init_f();