3 config CPU_V7_HAS_NONSEC
9 config ARCH_SUPPORT_PSCI
13 bool "Enable support for booting in non-secure mode" if EXPERT
14 depends on CPU_V7_HAS_NONSEC
17 Say Y here to enable support for booting in non-secure / SVC mode.
19 config ARMV7_BOOT_SEC_DEFAULT
20 bool "Boot in secure mode by default" if EXPERT
21 depends on ARMV7_NONSEC
22 default y if ARCH_TEGRA
24 Say Y here to boot in secure mode by default even if non-secure mode
25 is supported. This option is useful to boot kernels which do not
26 suppport booting in non-secure mode. Only set this if you need it.
27 This can be overridden at run-time by setting the bootm_boot_mode env.
28 variable to "sec" or "nonsec".
30 config HAS_ARMV7_SECURE_BASE
31 bool "Enable support for a ahardware secure memory area"
32 default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
33 || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
35 config ARMV7_SECURE_BASE
36 hex "Base address for secure mode memory"
37 depends on HAS_ARMV7_SECURE_BASE
38 default 0xfff00000 if TEGRA124
39 default 0x2ffc0000 if ARCH_STM32MP
40 default 0x2f000000 if ARCH_MX7ULP
41 default 0x10010000 if ARCH_LS1021A
42 default 0x00900000 if ARCH_MX7
43 default 0x00044000 if MACH_SUN8I
44 default 0x00020000 if MACH_SUN6I || MACH_SUN7I
46 config ARMV7_SECURE_RESERVE_SIZE
48 depends on TEGRA124 && HAS_ARMV7_SECURE_BASE
51 Reserve top 1M for secure RAM
53 config ARMV7_SECURE_MAX_SIZE
55 depends on ARMV7_SECURE_BASE && ARCH_STM32MP || MACH_SUN6I \
56 || MACH_SUN7I || MACH_SUN8I
57 default 0xbc00 if MACH_SUN8I && !MACH_SUN8I_H3
58 default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
62 bool "Enable support for hardware virtualization" if EXPERT
63 depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
66 Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
69 bool "Enable PSCI support" if EXPERT
70 depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
73 Say Y here to enable PSCI support.
76 prompt "Supported PSCI version"
78 default ARMV7_PSCI_0_1 if ARCH_SUNXI
79 default ARMV7_PSCI_1_0
81 Select the supported PSCI version.
93 config ARMV7_PSCI_NR_CPUS
94 int "Maximum supported CPUs for PSCI"
95 depends on ARMV7_NONSEC
98 The maximum number of CPUs supported in the PSCI firmware.
99 It is no problem to set a larger value than the number of
100 CPUs in the actual hardware implementation.
103 bool "Use LPAE page table format" if EXPERT
105 default y if ARMV7_VIRT
107 Say Y here to use the long descriptor page table format. This is
108 required if U-Boot runs in HYP mode.
110 config SPL_ARMV7_SET_CORTEX_SMPEN
113 Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.