1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for ARM926EJS CPU-core
5 * Copyright (c) 2003 Texas Instruments
7 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
9 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
10 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
11 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
12 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
13 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
17 #include <asm-offsets.h>
20 #include <linux/linkage.h>
23 *************************************************************************
25 * Startup Code (reset vector)
27 * do important init only if we don't start from memory!
28 * setup Memory and board specific bits prior to relocation.
29 * relocate armboot to ram
32 *************************************************************************
36 .globl save_boot_params_ret
37 .type save_boot_params_ret,%function
40 /* Allow the board to save important registers */
44 * set the cpu to SVC32 mode
52 * we do sys-critical inits only at reboot,
53 * not when booting from ram!
55 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
61 /*------------------------------------------------------------------------------*/
63 .globl c_runtime_cpu_setup
69 *************************************************************************
71 * CPU_init_critical registers
73 * setup important registers
76 *************************************************************************
78 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
81 * flush D cache before disabling it
85 mrc p15, 0, r15, c7, c10, 3
88 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
89 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
92 * disable MMU and D cache
93 * enable I cache if SYS_ICACHE_OFF is not defined
95 mrc p15, 0, r0, c1, c0, 0
96 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
97 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
98 #ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
99 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
101 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
103 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
104 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
105 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
107 mcr p15, 0, r0, c1, c0, 0
109 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
111 * Go setup Memory and board specific bits prior to relocation.
113 mov r4, lr /* perserve link reg across call */
114 bl lowlevel_init /* go setup pll,mux,memory */
115 mov lr, r4 /* restore link */
117 mov pc, lr /* back to my caller */
118 #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
120 /*************************************************************************
122 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
123 * __attribute__((weak));
125 * Stack pointer is not yet initialized at this moment
126 * Don't save anything to stack even if compiled with -O0
128 *************************************************************************/
129 WEAK(save_boot_params)
130 b save_boot_params_ret /* back to my caller */
131 ENDPROC(save_boot_params)