2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm-offsets.h>
39 #if defined(CONFIG_OMAP1610)
40 #include <./configs/omap1510.h>
41 #elif defined(CONFIG_OMAP730)
42 #include <./configs/omap730.h>
46 *************************************************************************
48 * Jump vector table as in table 3.1 in [1]
50 *************************************************************************
54 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
59 .word CONFIG_SYS_DV_NOR_BOOT_CFG
66 #ifdef CONFIG_SPL_BUILD
67 /* No exception handlers in preloader */
78 /* pad to 64 byte boundary */
87 ldr pc, _undefined_instruction
88 ldr pc, _software_interrupt
89 ldr pc, _prefetch_abort
95 _undefined_instruction:
96 .word undefined_instruction
98 .word software_interrupt
110 #endif /* CONFIG_SPL_BUILD */
111 .balignl 16,0xdeadbeef
115 *************************************************************************
117 * Startup Code (reset vector)
119 * do important init only if we don't start from memory!
120 * setup Memory and board specific bits prior to relocation.
121 * relocate armboot to ram
124 *************************************************************************
129 .word CONFIG_SYS_TEXT_BASE
132 * These are defined in the board-specific linker script.
133 * Subtracting _start from them lets the linker put their
134 * relative position in the executable instead of leaving
137 .globl _bss_start_ofs
139 .word __bss_start - _start
143 .word __bss_end__ - _start
149 #ifdef CONFIG_USE_IRQ
150 /* IRQ stack memory (calculated at run-time) */
151 .globl IRQ_STACK_START
155 /* IRQ stack memory (calculated at run-time) */
156 .globl FIQ_STACK_START
161 /* IRQ stack memory (calculated at run-time) + 8 bytes */
162 .globl IRQ_STACK_START_IN
167 * the actual reset code
172 * set the cpu to SVC32 mode
180 * we do sys-critical inits only at reboot,
181 * not when booting from ram!
183 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
187 /* Set stackpointer in internal RAM to call board_init_f */
189 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
190 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
194 /*------------------------------------------------------------------------------*/
197 * void relocate_code (addr_sp, gd, addr_moni)
199 * This "function" does not return, instead it continues in RAM
200 * after relocating the monitor code.
205 mov r4, r0 /* save addr_sp */
206 mov r5, r1 /* save addr of gd */
207 mov r6, r2 /* save addr of destination */
209 /* Set up the stack */
215 beq clear_bss /* skip relocation */
216 mov r1, r6 /* r1 <- scratch for copy loop */
217 ldr r3, _bss_start_ofs
218 add r2, r0, r3 /* r2 <- source end address */
221 ldmia r0!, {r9-r10} /* copy from source address [r0] */
222 stmia r1!, {r9-r10} /* copy to target address [r1] */
223 cmp r0, r2 /* until source end address [r2] */
226 #ifndef CONFIG_SPL_BUILD
228 * fix .rel.dyn relocations
230 ldr r0, _TEXT_BASE /* r0 <- Text base */
231 sub r9, r6, r0 /* r9 <- relocation offset */
232 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
233 add r10, r10, r0 /* r10 <- sym table in FLASH */
234 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
235 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
236 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
237 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
239 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
240 add r0, r0, r9 /* r0 <- location to fix up in RAM */
243 cmp r7, #23 /* relative fixup? */
245 cmp r7, #2 /* absolute fixup? */
247 /* ignore unknown type of fixup */
250 /* absolute fix: set location to (offset) symbol value */
251 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
252 add r1, r10, r1 /* r1 <- address of symbol in table */
253 ldr r1, [r1, #4] /* r1 <- symbol value */
254 add r1, r1, r9 /* r1 <- relocated sym addr */
257 /* relative fix: increase location by offset */
262 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
268 #ifndef CONFIG_SPL_BUILD
269 ldr r0, _bss_start_ofs
271 mov r4, r6 /* reloc addr */
274 mov r2, #0x00000000 /* clear */
276 clbss_l:str r2, [r0] /* clear loop... */
286 * We are done. Do not return, instead branch to second part of board
287 * initialization, now running from RAM.
289 #ifdef CONFIG_NAND_SPL
290 ldr r0, _nand_boot_ofs
296 ldr r0, _board_init_r_ofs
300 /* setup parameters for board_init_r */
301 mov r0, r5 /* gd_t */
302 mov r1, r6 /* dest_addr */
307 .word board_init_r - _start
311 .word __rel_dyn_start - _start
313 .word __rel_dyn_end - _start
315 .word __dynsym_start - _start
318 *************************************************************************
320 * CPU_init_critical registers
322 * setup important registers
323 * setup memory timing
325 *************************************************************************
327 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
330 * flush v4 I/D caches
333 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
334 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
337 * disable MMU stuff and caches
339 mrc p15, 0, r0, c1, c0, 0
340 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
341 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
342 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
343 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
344 mcr p15, 0, r0, c1, c0, 0
347 * Go setup Memory and board specific bits prior to relocation.
349 mov ip, lr /* perserve link reg across call */
350 bl lowlevel_init /* go setup pll,mux,memory */
351 mov lr, ip /* restore link */
352 mov pc, lr /* back to my caller */
353 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
355 #ifndef CONFIG_SPL_BUILD
357 *************************************************************************
361 *************************************************************************
367 #define S_FRAME_SIZE 72
389 #define MODE_SVC 0x13
393 * use bad_save_user_regs for abort/prefetch/undef/swi ...
394 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
397 .macro bad_save_user_regs
398 @ carve out a frame on current user stack
399 sub sp, sp, #S_FRAME_SIZE
400 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
401 ldr r2, IRQ_STACK_START_IN
402 @ get values for "aborted" pc and cpsr (into parm regs)
404 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
407 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
408 mov r0, sp @ save current stack into r0 (param register)
411 .macro irq_save_user_regs
412 sub sp, sp, #S_FRAME_SIZE
413 stmia sp, {r0 - r12} @ Calling r0-r12
414 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
416 stmdb r8, {sp, lr}^ @ Calling SP, LR
417 str lr, [r8, #0] @ Save calling PC
419 str r6, [r8, #4] @ Save CPSR
420 str r0, [r8, #8] @ Save OLD_R0
424 .macro irq_restore_user_regs
425 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
427 ldr lr, [sp, #S_PC] @ Get PC
428 add sp, sp, #S_FRAME_SIZE
429 subs pc, lr, #4 @ return & move spsr_svc into cpsr
433 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
435 str lr, [r13] @ save caller lr in position 0 of saved stack
436 mrs lr, spsr @ get the spsr
437 str lr, [r13, #4] @ save spsr in position 1 of saved stack
438 mov r13, #MODE_SVC @ prepare SVC-Mode
440 msr spsr, r13 @ switch modes, make sure moves will execute
441 mov lr, pc @ capture return pc
442 movs pc, lr @ jump to next instruction & switch modes.
445 .macro get_irq_stack @ setup IRQ stack
446 ldr sp, IRQ_STACK_START
449 .macro get_fiq_stack @ setup FIQ stack
450 ldr sp, FIQ_STACK_START
452 #endif /* CONFIG_SPL_BUILD */
457 #ifdef CONFIG_SPL_BUILD
460 ldr sp, _TEXT_BASE /* switch to abort stack */
462 bl 1b /* hang and never return */
463 #else /* !CONFIG_SPL_BUILD */
465 undefined_instruction:
468 bl do_undefined_instruction
474 bl do_software_interrupt
494 #ifdef CONFIG_USE_IRQ
501 irq_restore_user_regs
506 /* someone ought to write a more effiction fiq_save_user_regs */
509 irq_restore_user_regs
526 #endif /* CONFIG_SPL_BUILD */