arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX28 Boot PMIC init
   4  *
   5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   6  * on behalf of DENX Software Engineering GmbH
   7  */
   8
   9 #include <common.h>
  10 #include <config.h>
  11 #include <hang.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/imx-regs.h>
  15
  16 #include "mxs_init.h"
  17
  18 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
  19 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
  20                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
  21 #else
  22 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
  23                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
  24 #endif
  25 /**
  26  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
  27  *
  28  * This function switches the CPU core clock from PLL to 24MHz XTAL
  29  * oscilator. This is necessary if the PLL is being reconfigured to
  30  * prevent crash of the CPU core.
  31  */
  32 static void mxs_power_clock2xtal(void)
  33 {
  34         struct mxs_clkctrl_regs *clkctrl_regs =
  35                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  36
  37         debug("SPL: Switching CPU clock to 24MHz XTAL\n");
  38
  39         /* Set XTAL as CPU reference clock */
  40         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  41                 &clkctrl_regs->hw_clkctrl_clkseq_set);
  42 }
  43
  44 static void mxs_power_regs_dump(void)
  45 {
  46         struct mxs_power_regs *power_regs =
  47                 (struct mxs_power_regs *)MXS_POWER_BASE;
  48
  49         debug("ctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_ctrl));
  50         debug("5vctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_5vctrl));
  51         debug("minpwr:\t\t 0x%x\n", readl(&power_regs->hw_power_minpwr));
  52         debug("charge:\t\t 0x%x\n", readl(&power_regs->hw_power_charge));
  53         debug("vddctrl:\t 0x%x\n", readl(&power_regs->hw_power_vdddctrl));
  54         debug("vddactrl:\t 0x%x\n", readl(&power_regs->hw_power_vddactrl));
  55         debug("vddioctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddioctrl));
  56         debug("vddmemctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddmemctrl));
  57         debug("dcdc4p2:\t 0x%x\n", readl(&power_regs->hw_power_dcdc4p2));
  58         debug("misc:\t\t 0x%x\n", readl(&power_regs->hw_power_misc));
  59         debug("dclimits:\t 0x%x\n", readl(&power_regs->hw_power_dclimits));
  60         debug("loopctrl:\t 0x%x\n", readl(&power_regs->hw_power_loopctrl));
  61         debug("sts:\t\t 0x%x\n", readl(&power_regs->hw_power_sts));
  62         debug("speed:\t\t 0x%x\n", readl(&power_regs->hw_power_speed));
  63         debug("battmonitor:\t 0x%x\n",
  64               readl(&power_regs->hw_power_battmonitor));
  65 }
  66
  67 /**
  68  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
  69  *
  70  * This function switches the CPU core clock from 24MHz XTAL oscilator
  71  * to PLL. This can only be called once the PLL has re-locked and once
  72  * the PLL is stable after reconfiguration.
  73  */
  74 static void mxs_power_clock2pll(void)
  75 {
  76         struct mxs_clkctrl_regs *clkctrl_regs =
  77                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  78
  79         debug("SPL: Switching CPU core clock source to PLL\n");
  80
  81         /*
  82          * TODO: Are we really? It looks like we turn on PLL0, but we then
  83          * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
  84          * set by mxs_power_clock2xtal()). Clearing this bit here seems to
  85          * introduce some instability (causing the CPU core to hang). Maybe
  86          * we aren't giving PLL0 enough time to stabilise?
  87          */
  88         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
  89                         CLKCTRL_PLL0CTRL0_POWER);
  90         early_delay(100);
  91
  92         /*
  93          * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
  94          * wait on the PLL0 LOCK bit?
  95          */
  96         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
  97                         CLKCTRL_CLKSEQ_BYPASS_CPU);
  98 }
  99
 100 /**
 101  * mxs_power_set_auto_restart() - Set the auto-restart bit
 102  *
 103  * This function ungates the RTC block and sets the AUTO_RESTART
 104  * bit to work around a design bug on MX28EVK Rev. A .
 105  */
 106
 107 static void mxs_power_set_auto_restart(void)
 108 {
 109         struct mxs_rtc_regs *rtc_regs =
 110                 (struct mxs_rtc_regs *)MXS_RTC_BASE;
 111
 112         debug("SPL: Setting auto-restart bit\n");
 113
 114         writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
 115         while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
 116                 ;
 117
 118         writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
 119         while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
 120                 ;
 121
 122         /* Do nothing if flag already set */
 123         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
 124                 return;
 125
 126         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
 127                 ;
 128
 129         setbits_le32(&rtc_regs->hw_rtc_persistent0,
 130                         RTC_PERSISTENT0_AUTO_RESTART);
 131         writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
 132         writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
 133         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
 134                 ;
 135         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
 136                 ;
 137 }
 138
 139 /**
 140  * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
 141  *
 142  * This function configures the VDDIO, VDDA and VDDD linear regulators output
 143  * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
 144  * converter. This is the recommended setting for the case where we use both
 145  * linear regulators and DC-DC converter to power the VDDIO rail.
 146  */
 147 static void mxs_power_set_linreg(void)
 148 {
 149         struct mxs_power_regs *power_regs =
 150                 (struct mxs_power_regs *)MXS_POWER_BASE;
 151
 152         /* Set linear regulator 25mV below switching converter */
 153         debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
 154         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 155                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 156                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 157
 158         debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
 159         clrsetbits_le32(&power_regs->hw_power_vddactrl,
 160                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
 161                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
 162
 163         debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
 164         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 165                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
 166                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 167 }
 168
 169 /**
 170  * mxs_get_batt_volt() - Measure battery input voltage
 171  *
 172  * This function retrieves the battery input voltage and returns it.
 173  */
 174 static int mxs_get_batt_volt(void)
 175 {
 176         struct mxs_power_regs *power_regs =
 177                 (struct mxs_power_regs *)MXS_POWER_BASE;
 178         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
 179         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
 180         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
 181         volt *= 8;
 182
 183         debug("SPL: Battery Voltage = %dmV\n", volt);
 184         return volt;
 185 }
 186
 187 /**
 188  * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
 189  *
 190  * This function checks if the battery input voltage is higher than 3.6V and
 191  * therefore allows the system to successfully boot using this power source.
 192  */
 193 static int mxs_is_batt_ready(void)
 194 {
 195         return (mxs_get_batt_volt() >= 3600);
 196 }
 197
 198 /**
 199  * mxs_is_batt_good() - Test if battery is operational at all
 200  *
 201  * This function starts recharging the battery and tests if the input current
 202  * provided by the 5V input recharging the battery is also sufficient to power
 203  * the DC-DC converter.
 204  */
 205 static int mxs_is_batt_good(void)
 206 {
 207         struct mxs_power_regs *power_regs =
 208                 (struct mxs_power_regs *)MXS_POWER_BASE;
 209         uint32_t volt = mxs_get_batt_volt();
 210
 211         if ((volt >= 2400) && (volt <= 4300)) {
 212                 debug("SPL: Battery is good\n");
 213                 return 1;
 214         }
 215
 216         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 217                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 218                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 219         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 220                 &power_regs->hw_power_5vctrl_clr);
 221
 222         clrsetbits_le32(&power_regs->hw_power_charge,
 223                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 224                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
 225
 226         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
 227         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 228                 &power_regs->hw_power_5vctrl_clr);
 229
 230         early_delay(500000);
 231
 232         volt = mxs_get_batt_volt();
 233
 234         if (volt >= 3500) {
 235                 debug("SPL: Battery Voltage too high\n");
 236                 return 0;
 237         }
 238
 239         if (volt >= 2400) {
 240                 debug("SPL: Battery is good\n");
 241                 return 1;
 242         }
 243
 244         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 245                 &power_regs->hw_power_charge_clr);
 246         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 247
 248         debug("SPL: Battery Voltage too low\n");
 249         return 0;
 250 }
 251
 252 /**
 253  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
 254  *
 255  * This function enables the 5V detection comparator and sets the 5V valid
 256  * threshold to 4.4V . We use 4.4V threshold here to make sure that even
 257  * under high load, the voltage drop on the 5V input won't be so critical
 258  * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
 259  * converter and thus making the system crash.
 260  */
 261 static void mxs_power_setup_5v_detect(void)
 262 {
 263         struct mxs_power_regs *power_regs =
 264                 (struct mxs_power_regs *)MXS_POWER_BASE;
 265
 266         /* Start 5V detection */
 267         debug("SPL: Starting 5V input detection comparator\n");
 268         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 269                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
 270                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
 271                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
 272 }
 273
 274 /**
 275  * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
 276  * @freqsel:    One of the POWER_MISC_FREQSEL_xxx defines to select the clock
 277  *
 278  * This function configures and then enables an alternative PLL clock source
 279  * for the DC-DC converters.
 280  */
 281 void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
 282 {
 283         struct mxs_power_regs *power_regs =
 284                 (struct mxs_power_regs *)MXS_POWER_BASE;
 285
 286         /* Select clocksource for DC-DC converters */
 287         clrsetbits_le32(&power_regs->hw_power_misc,
 288                         POWER_MISC_FREQSEL_MASK,
 289                         freqsel);
 290         setbits_le32(&power_regs->hw_power_misc,
 291                         POWER_MISC_SEL_PLLCLK);
 292 }
 293
 294 /**
 295  * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
 296  *
 297  * Normally, there is no need to switch DC-DC clocksource. This is the reason,
 298  * why this function is a stub and does nothing. However, boards can implement
 299  * this function when required and call mxs_power_switch_dcdc_clocksource() to
 300  * switch to an alternative clock source.
 301  */
 302 __weak void mxs_power_setup_dcdc_clocksource(void)
 303 {
 304         debug("SPL: Using default DC-DC clocksource\n");
 305 }
 306
 307 /**
 308  * mxs_src_power_init() - Preconfigure the power block
 309  *
 310  * This function configures reasonable values for the DC-DC control loop
 311  * and battery monitor.
 312  */
 313 static void mxs_src_power_init(void)
 314 {
 315         struct mxs_power_regs *power_regs =
 316                 (struct mxs_power_regs *)MXS_POWER_BASE;
 317
 318         debug("SPL: Pre-Configuring power block\n");
 319
 320         /* Improve efficieny and reduce transient ripple */
 321         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
 322                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
 323
 324         clrsetbits_le32(&power_regs->hw_power_dclimits,
 325                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
 326                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
 327
 328         setbits_le32(&power_regs->hw_power_battmonitor,
 329                         POWER_BATTMONITOR_EN_BATADJ);
 330
 331         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
 332         clrsetbits_le32(&power_regs->hw_power_loopctrl,
 333                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
 334                         POWER_LOOPCTRL_RCSCALE_THRESH |
 335                         POWER_LOOPCTRL_EN_RCSCALE_8X);
 336
 337         clrsetbits_le32(&power_regs->hw_power_minpwr,
 338                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 339
 340         /* 5V to battery handoff ... FIXME */
 341         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 342         early_delay(30);
 343         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 344 }
 345
 346 /**
 347  * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
 348  *
 349  * This function configures the necessary parameters for the 4P2 linear
 350  * regulator to supply the DC-DC converter from 5V input.
 351  */
 352 static void mxs_power_init_4p2_params(void)
 353 {
 354         struct mxs_power_regs *power_regs =
 355                 (struct mxs_power_regs *)MXS_POWER_BASE;
 356
 357         debug("SPL: Configuring common 4P2 regulator params\n");
 358
 359         /* Setup 4P2 parameters */
 360         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 361                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
 362                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
 363
 364         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 365                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
 366                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
 367
 368         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 369                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
 370                 DCDC4P2_DROPOUT_CONFIG);
 371
 372         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 373                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 374                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 375 }
 376
 377 /**
 378  * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
 379  * @xfer:       Select if the input shall be enabled or disabled
 380  *
 381  * This function enables or disables the 4P2 input into the DC-DC converter.
 382  */
 383 static void mxs_enable_4p2_dcdc_input(int xfer)
 384 {
 385         struct mxs_power_regs *power_regs =
 386                 (struct mxs_power_regs *)MXS_POWER_BASE;
 387         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
 388         uint32_t prev_5v_brnout, prev_5v_droop;
 389
 390         debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
 391
 392         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
 393                         POWER_5VCTRL_ENABLE_DCDC)) {
 394                 return;
 395         }
 396
 397         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
 398                                 POWER_5VCTRL_PWDN_5VBRNOUT;
 399         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
 400                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
 401
 402         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 403         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 404                 &power_regs->hw_power_reset);
 405
 406         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
 407
 408         /*
 409          * Recording orignal values that will be modified temporarlily
 410          * to handle a chip bug. See chip errata for CQ ENGR00115837
 411          */
 412         tmp = readl(&power_regs->hw_power_5vctrl);
 413         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
 414         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
 415
 416         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
 417
 418         /*
 419          * Disable mechanisms that get erroneously tripped by when setting
 420          * the DCDC4P2 EN_DCDC
 421          */
 422         clrbits_le32(&power_regs->hw_power_5vctrl,
 423                 POWER_5VCTRL_VBUSVALID_5VDETECT |
 424                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
 425
 426         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
 427
 428         if (xfer) {
 429                 setbits_le32(&power_regs->hw_power_5vctrl,
 430                                 POWER_5VCTRL_DCDC_XFER);
 431                 early_delay(20);
 432                 clrbits_le32(&power_regs->hw_power_5vctrl,
 433                                 POWER_5VCTRL_DCDC_XFER);
 434
 435                 setbits_le32(&power_regs->hw_power_5vctrl,
 436                                 POWER_5VCTRL_ENABLE_DCDC);
 437         } else {
 438                 setbits_le32(&power_regs->hw_power_dcdc4p2,
 439                                 POWER_DCDC4P2_ENABLE_DCDC);
 440         }
 441
 442         early_delay(25);
 443
 444         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 445                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
 446
 447         if (vbus_5vdetect)
 448                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
 449
 450         if (!pwd_bo)
 451                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 452
 453         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
 454                 writel(POWER_CTRL_VBUS_VALID_IRQ,
 455                         &power_regs->hw_power_ctrl_clr);
 456
 457         if (prev_5v_brnout) {
 458                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 459                         &power_regs->hw_power_5vctrl_set);
 460                 writel(POWER_RESET_UNLOCK_KEY,
 461                         &power_regs->hw_power_reset);
 462         } else {
 463                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 464                         &power_regs->hw_power_5vctrl_clr);
 465                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 466                         &power_regs->hw_power_reset);
 467         }
 468
 469         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
 470                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
 471                         &power_regs->hw_power_ctrl_clr);
 472
 473         if (prev_5v_droop)
 474                 clrbits_le32(&power_regs->hw_power_ctrl,
 475                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 476         else
 477                 setbits_le32(&power_regs->hw_power_ctrl,
 478                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 479 }
 480
 481 /**
 482  * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
 483  *
 484  * This function enables the 4P2 regulator and switches the DC-DC converter
 485  * to use the 4P2 input.
 486  */
 487 static void mxs_power_init_4p2_regulator(void)
 488 {
 489         struct mxs_power_regs *power_regs =
 490                 (struct mxs_power_regs *)MXS_POWER_BASE;
 491         uint32_t tmp, tmp2;
 492
 493         debug("SPL: Enabling 4P2 regulator\n");
 494
 495         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
 496
 497         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
 498
 499         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 500                 &power_regs->hw_power_5vctrl_clr);
 501         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
 502
 503         /* Power up the 4p2 rail and logic/control */
 504         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 505                 &power_regs->hw_power_5vctrl_clr);
 506
 507         /*
 508          * Start charging up the 4p2 capacitor. We ramp of this charge
 509          * gradually to avoid large inrush current from the 5V cable which can
 510          * cause transients/problems
 511          */
 512         debug("SPL: Charging 4P2 capacitor\n");
 513         mxs_enable_4p2_dcdc_input(0);
 514
 515         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 516                 /*
 517                  * If we arrived here, we were unable to recover from mx23 chip
 518                  * errata 5837. 4P2 is disabled and sufficient battery power is
 519                  * not present. Exiting to not enable DCDC power during 5V
 520                  * connected state.
 521                  */
 522                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 523                         POWER_DCDC4P2_ENABLE_DCDC);
 524                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 525                         &power_regs->hw_power_5vctrl_set);
 526
 527                 debug("SPL: Unable to recover from mx23 errata 5837\n");
 528                 hang();
 529         }
 530
 531         /*
 532          * Here we set the 4p2 brownout level to something very close to 4.2V.
 533          * We then check the brownout status. If the brownout status is false,
 534          * the voltage is already close to the target voltage of 4.2V so we
 535          * can go ahead and set the 4P2 current limit to our max target limit.
 536          * If the brownout status is true, we need to ramp us the current limit
 537          * so that we don't cause large inrush current issues. We step up the
 538          * current limit until the brownout status is false or until we've
 539          * reached our maximum defined 4p2 current limit.
 540          */
 541         debug("SPL: Setting 4P2 brownout level\n");
 542         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 543                         POWER_DCDC4P2_BO_MASK,
 544                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
 545
 546         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
 547                 setbits_le32(&power_regs->hw_power_5vctrl,
 548                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 549         } else {
 550                 tmp = (readl(&power_regs->hw_power_5vctrl) &
 551                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
 552                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 553                 while (tmp < 0x3f) {
 554                         if (!(readl(&power_regs->hw_power_sts) &
 555                                         POWER_STS_DCDC_4P2_BO)) {
 556                                 tmp = readl(&power_regs->hw_power_5vctrl);
 557                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 558                                 early_delay(100);
 559                                 writel(tmp, &power_regs->hw_power_5vctrl);
 560                                 break;
 561                         } else {
 562                                 tmp++;
 563                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
 564                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 565                                 tmp2 |= tmp <<
 566                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 567                                 writel(tmp2, &power_regs->hw_power_5vctrl);
 568                                 early_delay(100);
 569                         }
 570                 }
 571         }
 572
 573         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 574         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 575 }
 576
 577 /**
 578  * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
 579  *
 580  * This function configures the DC-DC converter to be supplied from the 4P2
 581  * linear regulator.
 582  */
 583 static void mxs_power_init_dcdc_4p2_source(void)
 584 {
 585         struct mxs_power_regs *power_regs =
 586                 (struct mxs_power_regs *)MXS_POWER_BASE;
 587
 588         debug("SPL: Switching DC-DC converters to 4P2\n");
 589
 590         if (!(readl(&power_regs->hw_power_dcdc4p2) &
 591                 POWER_DCDC4P2_ENABLE_DCDC)) {
 592                 debug("SPL: Already switched - aborting\n");
 593                 hang();
 594         }
 595
 596         mxs_enable_4p2_dcdc_input(1);
 597
 598         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 599                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 600                         POWER_DCDC4P2_ENABLE_DCDC);
 601                 writel(POWER_5VCTRL_ENABLE_DCDC,
 602                         &power_regs->hw_power_5vctrl_clr);
 603                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 604                         &power_regs->hw_power_5vctrl_set);
 605         }
 606 }
 607
 608 /**
 609  * mxs_power_enable_4p2() - Power up the 4P2 regulator
 610  *
 611  * This function drives the process of powering up the 4P2 linear regulator
 612  * and switching the DC-DC converter input over to the 4P2 linear regulator.
 613  */
 614 static void mxs_power_enable_4p2(void)
 615 {
 616         struct mxs_power_regs *power_regs =
 617                 (struct mxs_power_regs *)MXS_POWER_BASE;
 618         uint32_t vdddctrl, vddactrl, vddioctrl;
 619         uint32_t tmp;
 620
 621         debug("SPL: Powering up 4P2 regulator\n");
 622
 623         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
 624         vddactrl = readl(&power_regs->hw_power_vddactrl);
 625         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
 626
 627         setbits_le32(&power_regs->hw_power_vdddctrl,
 628                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 629                 POWER_VDDDCTRL_PWDN_BRNOUT);
 630
 631         setbits_le32(&power_regs->hw_power_vddactrl,
 632                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 633                 POWER_VDDACTRL_PWDN_BRNOUT);
 634
 635         setbits_le32(&power_regs->hw_power_vddioctrl,
 636                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
 637
 638         mxs_power_init_4p2_params();
 639         mxs_power_init_4p2_regulator();
 640
 641         /* Shutdown battery (none present) */
 642         if (!mxs_is_batt_ready()) {
 643                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 644                                 POWER_DCDC4P2_BO_MASK);
 645                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
 646                                 &power_regs->hw_power_ctrl_clr);
 647                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
 648                                 &power_regs->hw_power_ctrl_clr);
 649         }
 650
 651         mxs_power_init_dcdc_4p2_source();
 652
 653         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 654         early_delay(20);
 655         writel(vddactrl, &power_regs->hw_power_vddactrl);
 656         early_delay(20);
 657         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 658
 659         /*
 660          * Check if FET is enabled on either powerout and if so,
 661          * disable load.
 662          */
 663         tmp = 0;
 664         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
 665                         POWER_VDDDCTRL_DISABLE_FET);
 666         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
 667                         POWER_VDDACTRL_DISABLE_FET);
 668         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
 669                         POWER_VDDIOCTRL_DISABLE_FET);
 670         if (tmp)
 671                 writel(POWER_CHARGE_ENABLE_LOAD,
 672                         &power_regs->hw_power_charge_clr);
 673
 674         debug("SPL: 4P2 regulator powered-up\n");
 675 }
 676
 677 /**
 678  * mxs_boot_valid_5v() - Boot from 5V supply
 679  *
 680  * This function configures the power block to boot from valid 5V input.
 681  * This is called only if the 5V is reliable and can properly supply the
 682  * CPU. This function proceeds to configure the 4P2 converter to be supplied
 683  * from the 5V input.
 684  */
 685 static void mxs_boot_valid_5v(void)
 686 {
 687         struct mxs_power_regs *power_regs =
 688                 (struct mxs_power_regs *)MXS_POWER_BASE;
 689
 690         debug("SPL: Booting from 5V supply\n");
 691
 692         /*
 693          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
 694          * disconnect event. FIXME
 695          */
 696         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
 697                 &power_regs->hw_power_5vctrl_set);
 698
 699         /* Configure polarity to check for 5V disconnection. */
 700         writel(POWER_CTRL_POLARITY_VBUSVALID |
 701                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
 702                 &power_regs->hw_power_ctrl_clr);
 703
 704         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
 705                 &power_regs->hw_power_ctrl_clr);
 706
 707         mxs_power_enable_4p2();
 708 }
 709
 710 /**
 711  * mxs_powerdown() - Shut down the system
 712  *
 713  * This function powers down the CPU completely.
 714  */
 715 static void mxs_powerdown(void)
 716 {
 717         struct mxs_power_regs *power_regs =
 718                 (struct mxs_power_regs *)MXS_POWER_BASE;
 719
 720         debug("Powering Down\n");
 721
 722         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
 723         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 724                 &power_regs->hw_power_reset);
 725 }
 726
 727 /**
 728  * mxs_batt_boot() - Configure the power block to boot from battery input
 729  *
 730  * This function configures the power block to boot from the battery voltage
 731  * supply.
 732  */
 733 static void mxs_batt_boot(void)
 734 {
 735         struct mxs_power_regs *power_regs =
 736                 (struct mxs_power_regs *)MXS_POWER_BASE;
 737
 738         debug("SPL: Configuring power block to boot from battery\n");
 739
 740         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 741         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
 742
 743         clrbits_le32(&power_regs->hw_power_dcdc4p2,
 744                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
 745         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
 746
 747         /* 5V to battery handoff. */
 748         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 749         early_delay(30);
 750         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 751
 752         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
 753
 754         clrsetbits_le32(&power_regs->hw_power_minpwr,
 755                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 756
 757         mxs_power_set_linreg();
 758
 759         clrbits_le32(&power_regs->hw_power_vdddctrl,
 760                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
 761
 762         clrbits_le32(&power_regs->hw_power_vddactrl,
 763                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
 764
 765         clrbits_le32(&power_regs->hw_power_vddioctrl,
 766                 POWER_VDDIOCTRL_DISABLE_FET);
 767
 768         setbits_le32(&power_regs->hw_power_5vctrl,
 769                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 770
 771         setbits_le32(&power_regs->hw_power_5vctrl,
 772                 POWER_5VCTRL_ENABLE_DCDC);
 773
 774         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 775                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 776                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 777
 778         if (CONFIG_IS_ENABLED(MXS_PMU_MINIMAL_VDD5V_CURRENT))
 779                 setbits_le32(&power_regs->hw_power_5vctrl,
 780                              POWER_5VCTRL_ILIMIT_EQ_ZERO);
 781
 782         if (CONFIG_IS_ENABLED(MXS_PMU_DISABLE_BATT_CHARGE)) {
 783                 writel(POWER_CHARGE_PWD_BATTCHRG,
 784                        &power_regs->hw_power_charge_set);
 785                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 786                        &power_regs->hw_power_5vctrl_set);
 787         }
 788
 789         if (CONFIG_IS_ENABLED(MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR))
 790                 mxs_power_enable_4p2();
 791 }
 792
 793 /**
 794  * mxs_handle_5v_conflict() - Test if the 5V input is reliable
 795  *
 796  * This function tests if the 5V input can reliably supply the system. If it
 797  * can, then proceed to configuring the system to boot from 5V source, otherwise
 798  * try booting from battery supply. If we can not boot from battery supply
 799  * either, shut down the system.
 800  */
 801 static void mxs_handle_5v_conflict(void)
 802 {
 803         struct mxs_power_regs *power_regs =
 804                 (struct mxs_power_regs *)MXS_POWER_BASE;
 805         uint32_t tmp;
 806
 807         debug("SPL: Resolving 5V conflict\n");
 808
 809         setbits_le32(&power_regs->hw_power_vddioctrl,
 810                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
 811
 812         for (;;) {
 813                 tmp = readl(&power_regs->hw_power_sts);
 814
 815                 if (tmp & POWER_STS_VDDIO_BO) {
 816                         /*
 817                          * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
 818                          * unreliable
 819                          */
 820                         debug("SPL: VDDIO has a brownout\n");
 821                         mxs_powerdown();
 822                         break;
 823                 }
 824
 825                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
 826                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
 827                         mxs_boot_valid_5v();
 828                         break;
 829                 } else {
 830                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
 831                         mxs_powerdown();
 832                         break;
 833                 }
 834
 835                 /*
 836                  * TODO: I can't see this being reached. We'll either
 837                  * powerdown or boot from a stable 5V supply.
 838                  */
 839                 if (tmp & POWER_STS_PSWITCH_MASK) {
 840                         debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
 841                         mxs_batt_boot();
 842                         break;
 843                 }
 844         }
 845 }
 846
 847 /**
 848  * mxs_5v_boot() - Configure the power block to boot from 5V input
 849  *
 850  * This function handles configuration of the power block when supplied by
 851  * a 5V input.
 852  */
 853 static void mxs_5v_boot(void)
 854 {
 855         struct mxs_power_regs *power_regs =
 856                 (struct mxs_power_regs *)MXS_POWER_BASE;
 857
 858         debug("SPL: Configuring power block to boot from 5V input\n");
 859
 860         /*
 861          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
 862          * but their implementation always returns 1 so we omit it here.
 863          */
 864         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 865                 debug("SPL: 5V VDD good\n");
 866                 mxs_boot_valid_5v();
 867                 return;
 868         }
 869
 870         early_delay(1000);
 871         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 872                 debug("SPL: 5V VDD good (after delay)\n");
 873                 mxs_boot_valid_5v();
 874                 return;
 875         }
 876
 877         debug("SPL: 5V VDD not good\n");
 878         mxs_handle_5v_conflict();
 879 }
 880
 881 /**
 882  * mxs_init_batt_bo() - Configure battery brownout threshold
 883  *
 884  * This function configures the battery input brownout threshold. The value
 885  * at which the battery brownout happens is configured to 3.0V in the code.
 886  */
 887 static void mxs_init_batt_bo(void)
 888 {
 889         struct mxs_power_regs *power_regs =
 890                 (struct mxs_power_regs *)MXS_POWER_BASE;
 891
 892         debug("SPL: Initialising battery brown-out level to 3.0V\n");
 893
 894         /* Brownout at 3V */
 895         clrsetbits_le32(&power_regs->hw_power_battmonitor,
 896                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
 897                 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
 898
 899         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 900         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 901 }
 902
 903 /**
 904  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
 905  *
 906  * This function turns off the VDDD linear regulator and therefore makes
 907  * the VDDD rail be supplied only by the DC-DC converter.
 908  */
 909 static void mxs_switch_vddd_to_dcdc_source(void)
 910 {
 911         struct mxs_power_regs *power_regs =
 912                 (struct mxs_power_regs *)MXS_POWER_BASE;
 913
 914         debug("SPL: Switching VDDD to DC-DC converters\n");
 915
 916         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 917                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 918                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 919
 920         clrbits_le32(&power_regs->hw_power_vdddctrl,
 921                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 922                 POWER_VDDDCTRL_DISABLE_STEPPING);
 923 }
 924
 925 /**
 926  * mxs_power_configure_power_source() - Configure power block source
 927  *
 928  * This function is the core of the power configuration logic. The function
 929  * selects the power block input source and configures the whole power block
 930  * accordingly. After the configuration is complete and the system is stable
 931  * again, the function switches the CPU clock source back to PLL. Finally,
 932  * the function switches the voltage rails to DC-DC converter.
 933  */
 934 static void mxs_power_configure_power_source(void)
 935 {
 936         int batt_ready, batt_good;
 937         struct mxs_power_regs *power_regs =
 938                 (struct mxs_power_regs *)MXS_POWER_BASE;
 939         struct mxs_lradc_regs *lradc_regs =
 940                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 941
 942         debug("SPL: Configuring power source\n");
 943
 944         mxs_power_setup_dcdc_clocksource();
 945         mxs_src_power_init();
 946
 947         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 948                 batt_ready = mxs_is_batt_ready();
 949                 if (batt_ready) {
 950                         /* 5V source detected, good battery detected. */
 951                         mxs_batt_boot();
 952                 } else {
 953                         batt_good = mxs_is_batt_good();
 954                         if (!batt_good) {
 955                                 /* 5V source detected, bad battery detected. */
 956                                 writel(LRADC_CONVERSION_AUTOMATIC,
 957                                         &lradc_regs->hw_lradc_conversion_clr);
 958                                 clrbits_le32(&power_regs->hw_power_battmonitor,
 959                                         POWER_BATTMONITOR_BATT_VAL_MASK);
 960                         }
 961                         mxs_5v_boot();
 962                 }
 963         } else {
 964                 /* 5V not detected, booting from battery. */
 965                 mxs_batt_boot();
 966         }
 967
 968         /*
 969          * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
 970          * from USB VBUS
 971          */
 972         mxs_power_clock2pll();
 973
 974         mxs_init_batt_bo();
 975
 976         mxs_switch_vddd_to_dcdc_source();
 977
 978 #ifdef CONFIG_MX23
 979         /* Fire up the VDDMEM LinReg now that we're all set. */
 980         debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
 981         writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
 982                 &power_regs->hw_power_vddmemctrl);
 983 #endif
 984 }
 985
 986 /**
 987  * mxs_enable_output_rail_protection() - Enable power rail protection
 988  *
 989  * This function enables overload protection on the power rails. This is
 990  * triggered if the power rails' voltage drops rapidly due to overload and
 991  * in such case, the supply to the powerrail is cut-off, protecting the
 992  * CPU from damage. Note that under such condition, the system will likely
 993  * crash or misbehave.
 994  */
 995 static void mxs_enable_output_rail_protection(void)
 996 {
 997         struct mxs_power_regs *power_regs =
 998                 (struct mxs_power_regs *)MXS_POWER_BASE;
 999
1000         debug("SPL: Enabling output rail protection\n");
1001
1002         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1003                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1004
1005         setbits_le32(&power_regs->hw_power_vdddctrl,
1006                         POWER_VDDDCTRL_PWDN_BRNOUT);
1007
1008         setbits_le32(&power_regs->hw_power_vddactrl,
1009                         POWER_VDDACTRL_PWDN_BRNOUT);
1010
1011         setbits_le32(&power_regs->hw_power_vddioctrl,
1012                         POWER_VDDIOCTRL_PWDN_BRNOUT);
1013 }
1014
1015 /**
1016  * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1017  *
1018  * This function tests if the VDDIO rail is supplied by linear regulator
1019  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1020  * returns 0 if powered by the DC-DC converter.
1021  */
1022 static int mxs_get_vddio_power_source_off(void)
1023 {
1024         struct mxs_power_regs *power_regs =
1025                 (struct mxs_power_regs *)MXS_POWER_BASE;
1026         uint32_t tmp;
1027
1028         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1029                 tmp = readl(&power_regs->hw_power_vddioctrl);
1030                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1031                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1032                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1033                                 return 1;
1034                         }
1035                 }
1036
1037                 if (!(readl(&power_regs->hw_power_5vctrl) &
1038                         POWER_5VCTRL_ENABLE_DCDC)) {
1039                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1040                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1041                                 return 1;
1042                         }
1043                 }
1044         }
1045
1046         return 0;
1047
1048 }
1049
1050 /**
1051  * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1052  *
1053  * This function tests if the VDDD rail is supplied by linear regulator
1054  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1055  * returns 0 if powered by the DC-DC converter.
1056  */
1057 static int mxs_get_vddd_power_source_off(void)
1058 {
1059         struct mxs_power_regs *power_regs =
1060                 (struct mxs_power_regs *)MXS_POWER_BASE;
1061         uint32_t tmp;
1062
1063         tmp = readl(&power_regs->hw_power_vdddctrl);
1064         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1065                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1066                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1067                         return 1;
1068                 }
1069         }
1070
1071         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1072                 if (!(readl(&power_regs->hw_power_5vctrl) &
1073                         POWER_5VCTRL_ENABLE_DCDC)) {
1074                         return 1;
1075                 }
1076         }
1077
1078         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1079                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1080                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1081                         return 1;
1082                 }
1083         }
1084
1085         return 0;
1086 }
1087
1088 struct mxs_vddx_cfg {
1089         uint32_t                *reg;
1090         uint8_t                 step_mV;
1091         uint16_t                lowest_mV;
1092         int                     (*powered_by_linreg)(void);
1093         uint32_t                trg_mask;
1094         uint32_t                bo_irq;
1095         uint32_t                bo_enirq;
1096         uint32_t                bo_offset_mask;
1097         uint32_t                bo_offset_offset;
1098 };
1099
1100 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1101         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
1102                                         hw_power_vddioctrl),
1103 #if defined(CONFIG_MX23)
1104         .step_mV                = 25,
1105 #else
1106         .step_mV                = 50,
1107 #endif
1108         .lowest_mV              = 2800,
1109         .powered_by_linreg      = mxs_get_vddio_power_source_off,
1110         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
1111         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
1112         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
1113         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1114         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1115 };
1116
1117 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1118         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
1119                                         hw_power_vdddctrl),
1120         .step_mV                = 25,
1121         .lowest_mV              = 800,
1122         .powered_by_linreg      = mxs_get_vddd_power_source_off,
1123         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
1124         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
1125         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
1126         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
1127         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1128 };
1129
1130 #ifdef CONFIG_MX23
1131 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1132         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
1133                                         hw_power_vddmemctrl),
1134         .step_mV                = 50,
1135         .lowest_mV              = 1700,
1136         .powered_by_linreg      = NULL,
1137         .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
1138         .bo_irq                 = 0,
1139         .bo_enirq               = 0,
1140         .bo_offset_mask         = 0,
1141         .bo_offset_offset       = 0,
1142 };
1143 #endif
1144
1145 /**
1146  * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1147  * @cfg:                Configuration data of the DC-DC converter rail
1148  * @new_target:         New target voltage of the DC-DC converter rail
1149  * @new_brownout:       New brownout trigger voltage
1150  *
1151  * This function configures the output voltage on the DC-DC converter rail.
1152  * The rail is selected by the @cfg argument. The new voltage target is
1153  * selected by the @new_target and the voltage is specified in mV. The
1154  * new brownout value is selected by the @new_brownout argument and the
1155  * value is also in mV.
1156  */
1157 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1158                                 uint32_t new_target, uint32_t new_brownout)
1159 {
1160         struct mxs_power_regs *power_regs =
1161                 (struct mxs_power_regs *)MXS_POWER_BASE;
1162         uint32_t cur_target, diff, bo_int = 0;
1163         uint32_t powered_by_linreg = 0;
1164         int adjust_up, tmp;
1165
1166         new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
1167                                          cfg->step_mV);
1168
1169         cur_target = readl(cfg->reg);
1170         cur_target &= cfg->trg_mask;
1171         cur_target *= cfg->step_mV;
1172         cur_target += cfg->lowest_mV;
1173
1174         adjust_up = new_target > cur_target;
1175         if (cfg->powered_by_linreg)
1176                 powered_by_linreg = cfg->powered_by_linreg();
1177
1178         if (adjust_up && cfg->bo_irq) {
1179                 if (powered_by_linreg) {
1180                         bo_int = readl(cfg->reg);
1181                         clrbits_le32(cfg->reg, cfg->bo_enirq);
1182                 }
1183                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1184         }
1185
1186         do {
1187                 if (abs(new_target - cur_target) > 100) {
1188                         if (adjust_up)
1189                                 diff = cur_target + 100;
1190                         else
1191                                 diff = cur_target - 100;
1192                 } else {
1193                         diff = new_target;
1194                 }
1195
1196                 diff -= cfg->lowest_mV;
1197                 diff /= cfg->step_mV;
1198
1199                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1200
1201                 if (powered_by_linreg ||
1202                         (readl(&power_regs->hw_power_sts) &
1203                                 POWER_STS_VDD5V_GT_VDDIO))
1204                         early_delay(500);
1205                 else {
1206                         for (;;) {
1207                                 tmp = readl(&power_regs->hw_power_sts);
1208                                 if (tmp & POWER_STS_DC_OK)
1209                                         break;
1210                         }
1211                 }
1212
1213                 cur_target = readl(cfg->reg);
1214                 cur_target &= cfg->trg_mask;
1215                 cur_target *= cfg->step_mV;
1216                 cur_target += cfg->lowest_mV;
1217         } while (new_target > cur_target);
1218
1219         if (cfg->bo_irq) {
1220                 if (adjust_up && powered_by_linreg) {
1221                         writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1222                         if (bo_int & cfg->bo_enirq)
1223                                 setbits_le32(cfg->reg, cfg->bo_enirq);
1224                 }
1225
1226                 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1227                                 new_brownout << cfg->bo_offset_offset);
1228         }
1229 }
1230
1231 /**
1232  * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1233  *
1234  * This function starts and configures the LRADC block. This allows the
1235  * power initialization code to measure battery voltage and based on this
1236  * knowledge, decide whether to boot at all, boot from battery or boot
1237  * from 5V input.
1238  */
1239 static void mxs_setup_batt_detect(void)
1240 {
1241         debug("SPL: Starting battery voltage measurement logic\n");
1242
1243         mxs_lradc_init();
1244         mxs_lradc_enable_batt_measurement();
1245         early_delay(10);
1246 }
1247
1248 /**
1249  * mxs_ungate_power() - Ungate the POWER block
1250  *
1251  * This function ungates clock to the power block. In case the power block
1252  * was still gated at this point, it will not be possible to configure the
1253  * block and therefore the power initialization would fail. This function
1254  * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1255  */
1256 static void mxs_ungate_power(void)
1257 {
1258 #ifdef CONFIG_MX23
1259         struct mxs_power_regs *power_regs =
1260                 (struct mxs_power_regs *)MXS_POWER_BASE;
1261
1262         writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1263 #endif
1264 }
1265
1266 /**
1267  * mxs_power_init() - The power block init main function
1268  *
1269  * This function calls all the power block initialization functions in
1270  * proper sequence to start the power block.
1271  */
1272 void mxs_power_init(void)
1273 {
1274         struct mxs_power_regs *power_regs =
1275                 (struct mxs_power_regs *)MXS_POWER_BASE;
1276
1277         debug("SPL: Initialising Power Block\n");
1278
1279         mxs_ungate_power();
1280
1281         mxs_power_clock2xtal();
1282         mxs_power_set_auto_restart();
1283         mxs_power_set_linreg();
1284         mxs_power_setup_5v_detect();
1285
1286         mxs_setup_batt_detect();
1287
1288         mxs_power_configure_power_source();
1289         mxs_enable_output_rail_protection();
1290
1291         debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
1292         mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
1293
1294         debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n");
1295         mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400);
1296 #ifdef CONFIG_MX23
1297         debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
1298         mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
1299 #endif
1300         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1301                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1302                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1303                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1304
1305         writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
1306         mxs_power_regs_dump();
1307
1308         early_delay(1000);
1309 }
1310
1311 #ifdef  CONFIG_SPL_MXS_PSWITCH_WAIT
1312 /**
1313  * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1314  *
1315  * This function waits until the power-switch was pressed to start booting
1316  * the board.
1317  */
1318 void mxs_power_wait_pswitch(void)
1319 {
1320         struct mxs_power_regs *power_regs =
1321                 (struct mxs_power_regs *)MXS_POWER_BASE;
1322
1323         debug("SPL: Waiting for power switch input\n");
1324         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1325                 ;
1326 }
1327 #endif