2 * Freescale i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/imx-regs.h>
35 #include <asm/arch/sys_proto.h>
37 /* 1 second delay should be plenty of time for block reset. */
38 #define RESET_MAX_TIMEOUT 1000000
40 #define MX28_BLOCK_SFTRST (1 << 31)
41 #define MX28_BLOCK_CLKGATE (1 << 30)
43 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
44 inline void lowlevel_init(void) {}
46 void reset_cpu(ulong ignored) __attribute__((noreturn));
48 void reset_cpu(ulong ignored)
51 struct mx28_rtc_regs *rtc_regs =
52 (struct mx28_rtc_regs *)MXS_RTC_BASE;
54 /* Wait 1 uS before doing the actual watchdog reset */
55 writel(1, &rtc_regs->hw_rtc_watchdog);
56 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
58 /* Endless loop, reset will exit from here */
63 int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
66 if ((readl(®->reg) & mask) == mask)
74 int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
77 if ((readl(®->reg) & mask) == 0)
85 int mx28_reset_block(struct mx28_register *reg)
88 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
90 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
94 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
97 writel(MX28_BLOCK_SFTRST, ®->reg_set);
99 /* Wait for CLKGATE being set */
100 if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
104 writel(MX28_BLOCK_SFTRST, ®->reg_clr);
106 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
110 writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
112 if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
118 #ifdef CONFIG_ARCH_CPU_INIT
119 int arch_cpu_init(void)
121 struct mx28_clkctrl_regs *clkctrl_regs =
122 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
127 /* Clear bypass bit */
128 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
129 &clkctrl_regs->hw_clkctrl_clkseq_set);
131 /* Set GPMI clock to ref_gpmi / 12 */
132 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
133 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
141 #if defined(CONFIG_DISPLAY_CPUINFO)
142 int print_cpuinfo(void)
144 printf("Freescale i.MX28 family\n");
149 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
151 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
152 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
153 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
154 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
159 * Initializes on-chip ethernet controllers.
161 #ifdef CONFIG_CMD_NET
162 int cpu_eth_init(bd_t *bis)
164 struct mx28_clkctrl_regs *clkctrl_regs =
165 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
167 /* Turn on ENET clocks */
168 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
169 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
171 /* Set up ENET PLL for 50 MHz */
172 /* Power on ENET PLL */
173 writel(CLKCTRL_PLL2CTRL0_POWER,
174 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
178 /* Gate on ENET PLL */
179 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
180 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
182 /* Enable pad output */
183 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
190 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,