2 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
3 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
29 #include <asm/arch/mxcmmc.h>
33 * get the system pll clock in Hz
35 * mfi + mfn / (mfd +1)
36 * f = 2 * f_ref * --------------------
39 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
41 unsigned int mfi = (pll >> 10) & 0xf;
42 unsigned int mfn = pll & 0x3ff;
43 unsigned int mfd = (pll >> 16) & 0x3ff;
44 unsigned int pd = (pll >> 26) & 0xf;
46 mfi = mfi <= 5 ? 5 : mfi;
48 return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
49 (mfd + 1) * (pd + 1));
52 static ulong clk_in_32k(void)
54 return 1024 * CONFIG_MX27_CLK32;
57 static ulong clk_in_26m(void)
59 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
61 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
63 return 26000000 * 2 / 3;
69 static ulong imx_get_mpllclk(void)
71 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
72 ulong cscr = readl(&pll->cscr);
75 if (cscr & CSCR_MCU_SEL)
80 return imx_decode_pll(readl(&pll->mpctl0), fref);
83 static ulong imx_get_armclk(void)
85 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
86 ulong cscr = readl(&pll->cscr);
87 ulong fref = imx_get_mpllclk();
90 if (!(cscr & CSCR_ARM_SRC_MPLL))
91 fref = lldiv((fref * 2), 3);
93 div = ((cscr >> 12) & 0x3) + 1;
95 return lldiv(fref, div);
98 static ulong imx_get_ahbclk(void)
100 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
101 ulong cscr = readl(&pll->cscr);
102 ulong fref = imx_get_mpllclk();
105 div = ((cscr >> 8) & 0x3) + 1;
107 return lldiv(fref * 2, 3 * div);
110 static __attribute__((unused)) ulong imx_get_spllclk(void)
112 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
113 ulong cscr = readl(&pll->cscr);
116 if (cscr & CSCR_SP_SEL)
121 return imx_decode_pll(readl(&pll->spctl0), fref);
124 static ulong imx_decode_perclk(ulong div)
126 return lldiv((imx_get_mpllclk() * 2), (div * 3));
129 static ulong imx_get_perclk1(void)
131 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
133 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
136 static ulong imx_get_perclk2(void)
138 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
140 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
143 static __attribute__((unused)) ulong imx_get_perclk3(void)
145 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
147 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
150 static __attribute__((unused)) ulong imx_get_perclk4(void)
152 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
154 return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
157 unsigned int mxc_get_clock(enum mxc_clock clk)
161 return imx_get_armclk();
163 return imx_get_ahbclk()/2;
165 return imx_get_perclk1();
167 return imx_get_ahbclk();
169 return imx_get_perclk2();
175 #if defined(CONFIG_DISPLAY_CPUINFO)
176 int print_cpuinfo (void)
180 printf("CPU: Freescale i.MX27 at %s MHz\n\n",
181 strmhz(buf, imx_get_mpllclk()));
186 int cpu_eth_init(bd_t *bis)
188 #if defined(CONFIG_FEC_MXC)
189 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
191 /* enable FEC clock */
192 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
193 writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
194 return fecmxc_initialize(bis);
201 * Initializes on-chip MMC controllers.
202 * to override, implement board_mmc_init()
204 int cpu_mmc_init(bd_t *bis)
206 #ifdef CONFIG_MXC_MMC
207 return mxc_mmc_init(bis);
213 void imx_gpio_mode(int gpio_mode)
215 struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
216 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
217 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
218 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
219 unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
220 unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
224 if (gpio_mode & GPIO_PUEN) {
225 writel(readl(®s->port[port].puen) | (1 << pin),
226 ®s->port[port].puen);
228 writel(readl(®s->port[port].puen) & ~(1 << pin),
229 ®s->port[port].puen);
233 if (gpio_mode & GPIO_OUT) {
234 writel(readl(®s->port[port].gpio_dir) | 1 << pin,
235 ®s->port[port].gpio_dir);
237 writel(readl(®s->port[port].gpio_dir) & ~(1 << pin),
238 ®s->port[port].gpio_dir);
241 /* Primary / alternate function */
242 if (gpio_mode & GPIO_AF) {
243 writel(readl(®s->port[port].gpr) | (1 << pin),
244 ®s->port[port].gpr);
246 writel(readl(®s->port[port].gpr) & ~(1 << pin),
247 ®s->port[port].gpr);
251 if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
252 writel(readl(®s->port[port].gius) | (1 << pin),
253 ®s->port[port].gius);
255 writel(readl(®s->port[port].gius) & ~(1 << pin),
256 ®s->port[port].gius);
259 /* Output / input configuration */
261 tmp = readl(®s->port[port].ocr1);
262 tmp &= ~(3 << (pin * 2));
263 tmp |= (ocr << (pin * 2));
264 writel(tmp, ®s->port[port].ocr1);
266 writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)),
267 ®s->port[port].iconfa1);
268 writel(readl(®s->port[port].iconfa1) | aout << (pin * 2),
269 ®s->port[port].iconfa1);
270 writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)),
271 ®s->port[port].iconfb1);
272 writel(readl(®s->port[port].iconfb1) | bout << (pin * 2),
273 ®s->port[port].iconfb1);
277 tmp = readl(®s->port[port].ocr2);
278 tmp &= ~(3 << (pin * 2));
279 tmp |= (ocr << (pin * 2));
280 writel(tmp, ®s->port[port].ocr2);
282 writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)),
283 ®s->port[port].iconfa2);
284 writel(readl(®s->port[port].iconfa2) | aout << (pin * 2),
285 ®s->port[port].iconfa2);
286 writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)),
287 ®s->port[port].iconfb2);
288 writel(readl(®s->port[port].iconfb2) | bout << (pin * 2),
289 ®s->port[port].iconfb2);
293 #ifdef CONFIG_MXC_UART
294 void mx27_uart1_init_pins(void)
297 unsigned int mode[] = {
302 for (i = 0; i < ARRAY_SIZE(mode); i++)
303 imx_gpio_mode(mode[i]);
306 #endif /* CONFIG_MXC_UART */
308 #ifdef CONFIG_FEC_MXC
309 void mx27_fec_init_pins(void)
312 unsigned int mode[] = {
322 PD9_AIN_FEC_MDC | GPIO_PUEN,
324 PD11_AOUT_FEC_TX_CLK,
333 for (i = 0; i < ARRAY_SIZE(mode); i++)
334 imx_gpio_mode(mode[i]);
337 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
340 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
341 struct fuse_bank *bank = &iim->bank[0];
342 struct fuse_bank0_regs *fuse =
343 (struct fuse_bank0_regs *)bank->fuse_regs;
345 for (i = 0; i < 6; i++)
346 mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
348 #endif /* CONFIG_FEC_MXC */
350 #ifdef CONFIG_MXC_MMC
351 void mx27_sd1_init_pins(void)
354 unsigned int mode[] = {
363 for (i = 0; i < ARRAY_SIZE(mode); i++)
364 imx_gpio_mode(mode[i]);
368 void mx27_sd2_init_pins(void)
371 unsigned int mode[] = {
380 for (i = 0; i < ARRAY_SIZE(mode); i++)
381 imx_gpio_mode(mode[i]);
384 #endif /* CONFIG_MXC_MMC */
386 #ifndef CONFIG_SYS_DCACHE_OFF
387 void enable_caches(void)
389 /* Enable D-cache. I-cache is already enabled in start.S */
392 #endif /* CONFIG_SYS_DCACHE_OFF */